Low noise, high power pseudomorphic HEMT

Claim 2

A transistor comprising a source and a drain, a heterostructure including a narrow bandgap channel layer coupling said source to said drain and in which a quantum well is formed to confine electrons, a first wider bandgap donor layer for supplying said electrons to said quantum well, and a first spacer layer disposed between said donor and channel layer, and a gate contact structure for applying voltage to said heterostructure to control the flow of electrons in said channel between said source and said drain, characterized in that said channel layer comprises InGaAs, said first donor layer comprises In y Ga 1-y P and said first spacer layer comprises a first outer spacer layer adjacent said donor layer and a first inner spacer layer adjacent said channel layer, said outer spacer layer comprising undoped In 0 .5-q (Al x Ga 1-x ) 0 .5+q P, and said inner spacer layer comprising undoped Al r Ga 1-r As, said channel layer and said inner spacer layer forming a pseudomorphic heterojunction at the interface between them.

Claim 3

The invention of claim 1 wherein 0.2≦x, 0.15≦y≦0.85,0≦r≦0.3, and 0≦q≦0.35, approximately.

Claim 4

The invention of claim 1 wherein said heterostructure includes a second wider bandgap donor layer for supplying said electrons to said quantum well, and a second spacer layer disposed between said channel layer and said second donor layer, said first and second donor layers being disposed on opposite sides of said channel layer, and further characterized in that said second spacer layer also comprises a second outer spacer layer adjacent said second donor layer and a second inner spacer layer adjacent said channel layer, said second outer spacer layer comprising undoped In 0 .5-q (Al x Ga 1-x ) 0 .5+q P, said second inner spacer layer comprising in Al r Ga 1-r As, and said second donor layer also comprising In y Ga 1-y P.

Claim 5

The invention of claim 3 wherein 0.2≦x, 0.15≦y≦0.85, 0≦r≦0.3, and 0≦q≦0.35, approximately.

Claim 6

The invention of claim 1 wherein said gate contact structure includes a gate electrode and a third wide bandgap layer forming a Schottky barrier with said electrode, further characterized in that said third layer also comprises In 0 .5-q (Al x Ga 1-x ) 0 .5+q P in which 0.2≦x and 0≦q≦0.35 approximately.

Claim 7

The invention of claim 5 wherein the composition of said third layer produces a Schottky barrier height of about 1.0 eV.

Claim 8

The invention of claim 3 wherein said channel layer comprises an In 0 .2 Ga 0 .8 As i-type layer and each of said donor layers comprises an In 0 .5 Ga 0 .5 P n-type layer.

Claim 9

A high electron mobility transistor comprising a source and a drain, a heterostructure comprising an i-type In 0 .2 Ga 0 .8 As channel layer coupling said source to said drain and in which a quantum well is formed for confining electrons, a pair of In y Ga 1-y P (0.15<y<0.85) Si-doped, n-type donor layers disposed on opposite sides of said channel layer for supplying said electrons to said quantum well, a pair of In 0 .5-q (Al x Ga 1-x ) 0 .5+q P (0≦q≦0.35 and 0.2≦x approximately) i-type outer spacer layers, an outer spacer layer disposed between said channel layer and each of said donor layers, and a pair of Al r Ga 1-r As (0≦r≦0.3) i-type inner spacer layers, an inner spacer layer disposed between each of said outer spacer layers and said channel layer, and a gate contact structure for applying voltage to said heterostructure including a Si-doped, n-type GaAs contact layer having and opening therein, a gate electrode disposed in said opening, and an i-type In 0 .5-q (Al x Ga 1-x ) 0 .5+q P layer forming a Schottky barrier with said gate electrode, wherein 0.2≦x and 0≦q≦0.35 approximately.

Claim 10

A high electron mobility transistor comprising a source and a drain, a heterostructure comprising an i-type In 0 .2 Ga 0 .8 As channel layer coupling said source to said drain and in which a quantum well is formed for confining electrons, a pair of In y Ga 1-y P (0.15<y<0.85) Si-doped, n-type donor layers disposed on opposite sides of said channel layer for supplying said electrons to said quantum well, a pair of In 0 .5-q (Al x Ga 1-x ) 0 .5+q P (0≦q≦0.35 and 0.2≦x approximately) i-type outer spacer layers, an outer spacer layer disposed between said channel layer and each of said donor layers, and a pair of Al r Ga 1-r As (0≦r≦0.3) i-type inner spacer layers, an inner spacer layer disposed between each of said outer spacer layers and said channel layer, and a gate contact structure for applying voltage to said heterostructure including a Si-doped, n-type GaAs contact layer having and opening therein, a gate electrode disposed in said opening, and an i-type In 0 .5-q (Al x Ga 1-x ) 0 .5+q P layer forming a Schottky barrier with said gate electrode, wherein 0.2≦x and 0≦q≦0.35 approximately.

Claim 11

The invention of claim 8 wherein the mole fraction of Al in said i-type layer produces a Schottky barrier height of at least about 1.0 eV.

Claim 12

The invention of claim 8 wherein said outer spacer layers comprise In 0 .5-q (Al 0 .2 Ga 0 .8) 0 .5+q P.

Claim 13

The invention of claim 10 wherein q=0.

Claim 14

An integrated circuit comprising a high power transistor, and a low noise transistor, each of said transistors comprising a source and a drain, a heterostructure including a narrow bandgap channel layer coupling said source to said drain and in which a quantum well is formed to confine electrons, a first wider bandgap donor layer for supplying said electrons to said quantum well, and a first spacer layer disposed between said donor and channel layers, and a gate contact structure for applying voltage to said heterostructure to control the flow of electrons in said channel between said source and said drain, characterized in that said channel layer comprises InGaAs, said first donor layer comprises In y Ga 1-y P and said first spacer layer comprises a first outer spacer layer adjacent said donor layer and a first inner spacer layer adjacent said channel layer, said outer spacer layer comprising undoped In 0 .5-q (Al x Ga 1-x ) 0 .5+q P, and said inner spacer layer comprising undoped Al r Ga 1-r As, said channel layer and said inner spacer layer forming a pseudomorphic heterojunction at the interface between them.

Claim 15

An integrated circuit comprising a high power transistor, and a low noise transistor, each of said transistors comprising a source and a drain, a heterostructure including a narrow bandgap channel layer coupling said source to said drain and in which a quantum well is formed to confine electrons, a first wider bandgap donor layer for supplying said electrons to said quantum well, and a first spacer layer disposed between said donor and channel layers, and a gate contact structure for applying voltage to said heterostructure to control the flow of electrons in said channel between said source and said drain, characterized in that said channel layer comprises InGaAs, said first donor layer comprises In y Ga 1-y P and said first spacer layer comprises a first outer spacer layer adjacent said donor layer and a first inner spacer layer adjacent said channel layer, said outer spacer layer comprising undoped In 0 .5-q (Al x Ga 1-x ) 0 .5+q P, and said inner spacer layer comprising undoped Al r Ga 1-r As, said channel layer and said inner spacer layer forming a pseudomorphic heterojunction at the interface between them.

Claim 16

The invention of claim 12 wherein 0.2≦x, 0.15≦y≦0.85, 0≦r≦0.3, and 0≦q≦0.35, approximately.