US4742379A
Expired / Lapsed
US
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HEMT with etch-stop
Assignee: Fujitsu Ltd
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Filing: 1984-11-29
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Granted: 1988-05-03
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Expires: 2004-11-29
Abstract
Abstract A compound semiconductor device comprises an enhancement-mode transistor and a depletion-mode transistor, each of which has a heterojunction and utilizes a two-dimensional electron gas. The method of producing the device comprises the steps of: forming an undoped GaAs channel layer on a semi-insulating GaAs substrate; forming an N-type AlGaAs electron-supply layer so as to form the heterojunction; forming an N-type GaAs layer; forming an AlGaAs layer; selectively etching the AlGaAs layer to form a recess; performing an etching treatment using an etchant which can etch rapidly GaAs and etch slowly AlGaAs to form simultaneously grooves for gate electrodes of the enhancement-mode transistor and the depletion-mode transistor, the bottoms of the grooves being in the N-type AlGaAs layer and the distance between the bottoms being equal to the thickness of the AlGaAs layer; and forming simultaneously the gate electrodes in the grooves.
Inventors
- 👤 Yoshimi Yamashita
- 👤 Kinjiro Kosemura
- 👤 Hidetoshi Ishiwari
- 👤 Sumio Yamamoto
- 👤 Shigeru Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/03; H10D84/038; H10D84/05; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/246; Y; Y10; Y10S; Y10S148/00; Y10S148/131; Y10S148/168
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
177 words
A semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor, has a heterojunction, and utilizes a two-dimensional electron gas, comprising: a semi-insulating compound semiconductor substrate; a semiconductor channel layer which is formed on said substrate and in which the two-dimensional electron gas is generated; an electron-supply layer formed on said semiconductor layer, which layers form the heterojunction; a first semiconductor layer formed on said electron-supply layer and having a composition different from said electron-supply layer; a second semiconductor layer formed on said first semiconductor layer, having a thickness for providing a predetermined difference of the threshold voltage between the enhancement-mode transistor and the depletion-mode transistor, said second semiconductor layer having a composition different from said first semiconductor layer and having an etching rate for a certain etchant the same as that of the composition of said electron-supply layer; a gate electrode of the depletion-mode transistor located on said electron-supply layer; and a gate electrode of the enhancement-mode transistor extending into said electron-supply layer by a depth corresponding to the thickness of said second semiconductor layer.
Claim 2
Dependent Claim
177 words
A semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor, has a heterojunction, and utilizes a two-dimensional electron gas, comprising: a semi-insulating compound semiconductor substrate; a semiconductor channel layer which is formed on said substrate and in which the two-dimensional electron gas is generated; an electron-supply layer formed on said semiconductor layer, which layers form the heterojunction; a first semiconductor layer formed on said electron-supply layer and having a composition different from said electron-supply layer; a second semiconductor layer formed on said first semiconductor layer, having a thickness for providing a predetermined difference of the threshold voltage between the enhancement-mode transistor and the depletion-mode transistor, said second semiconductor layer having a composition different from said first semiconductor layer and having an etching rate for a certain etchant the same as that of the composition of said electron-supply layer; a gate electrode of the depletion-mode transistor located on said electron-supply layer; and a gate electrode of the enhancement-mode transistor extending into said electron-supply layer by a depth corresponding to the thickness of said second semiconductor layer.
Claim 3
Dependent Claim
41 words
A semiconductor device according to claim 1, wherein said first semiconductor layer is composed of a composition that has an etching rate substantially higher than that of the composition of said electron-supply layer and second semiconductor layer for the same etchant.
Claim 4
Dependent Claim
32 words
A semiconductor device according to claim 1, wherein said semiconductor channel layer and said first semiconductor layer are of a material selected from the group consisting of gallium-arsenide, germanium, indium-antimonide, and indium-arsenide.
Claim 5
Dependent Claim
31 words
A semiconductor device according to claim 1, wherein said electron-supply layer and said second semiconductor layer are of a material selected from the group consisting of aluminum-gallium-arsenide, gallium-arsenide, cadmium-telluride, and gallium-antimonide.
Claim 6
Dependent Claim
45 words
A semiconductor device according to claim 1, wherein said substrate is of semi-insulating gallium-arsenic, said semiconductor channel layer is of undoped gallium-arsenide, said electron-supply layer is of N-type aluminum-gallium-arsenide, said first semiconductor layer is of N-type gallium-arsenide, and said second semiconductor layer is of aluminum-gallium-arsenide.
Claim 7
Dependent Claim
18 words
A semiconductor device according to claim 1, further comprising a cap layer formed on said second semiconductor layer.
Claim 8
Dependent Claim
14 words
A semiconductor device according to claim 6, wherein said cap layer is of gallium-arsenide.
Claim 9
Dependent Claim
320 words
A semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor, has a heterojunction, and utilizes a two-dimensional electron gas, comprising: a semi-insulating compound semiconductor substrate; (40); a semiconductor channel layer which (41) is formed on said substrate and in which the two-dimensional electron gas is generated; an electron-supply layer (42) formed on said semiconductor channel layer (41) which layers (41 and 42) form the heterojunction; a third doped semiconductor layer (43) formed on said electron-supply layer (42), having a composition different from said electron-supply layer; a fourth doped semiconductor layer (44) formed on said third semiconductor layer (43) and being composed of a composition that has the same etching rate as that of the composition of the electron-supply layer (42) for a certain etchant, the total thickness of the third and fourth semiconductor layers (43, 44) providing a predetermined difference of the threshold voltage between the enhancement-mode transistor and the depletion-mode transistor; a first semiconductor layer (45) formed on the fourth semiconductor layer (44) and being composed of a composition that has the same etching rate as that of the composition of the third semiconductor layer (43) for the same etchant; a second semiconductor layer (46) formed on said first semiconductor layer (45) and having a composition that has the same etching rate as the fourth semiconductor layer for the same etchant; a gate electrode (59) of the depletion-mode transistor being located on said fourth semiconductor layer (44); a gate electrode (58) of the enhancement-mode transistor being located on said electron supply layer (42) such that said gate electrode (58) of the enhancement-mode transistor extends further than said gate electrode (59) of said depletion-mode transistor by a distance substantially equal to said total thickness of said third and fourth semiconductor layers (43, 44); and contact electrodes (51a, 51b, 51c) being formed on said first semiconductor layer (45) at both sides of each of the gate electrodes (58, 59).
Claim 10
Dependent Claim
320 words
A semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor, has a heterojunction, and utilizes a two-dimensional electron gas, comprising: a semi-insulating compound semiconductor substrate; (40); a semiconductor channel layer which (41) is formed on said substrate and in which the two-dimensional electron gas is generated; an electron-supply layer (42) formed on said semiconductor channel layer (41) which layers (41 and 42) form the heterojunction; a third doped semiconductor layer (43) formed on said electron-supply layer (42), having a composition different from said electron-supply layer; a fourth doped semiconductor layer (44) formed on said third semiconductor layer (43) and being composed of a composition that has the same etching rate as that of the composition of the electron-supply layer (42) for a certain etchant, the total thickness of the third and fourth semiconductor layers (43, 44) providing a predetermined difference of the threshold voltage between the enhancement-mode transistor and the depletion-mode transistor; a first semiconductor layer (45) formed on the fourth semiconductor layer (44) and being composed of a composition that has the same etching rate as that of the composition of the third semiconductor layer (43) for the same etchant; a second semiconductor layer (46) formed on said first semiconductor layer (45) and having a composition that has the same etching rate as the fourth semiconductor layer for the same etchant; a gate electrode (59) of the depletion-mode transistor being located on said fourth semiconductor layer (44); a gate electrode (58) of the enhancement-mode transistor being located on said electron supply layer (42) such that said gate electrode (58) of the enhancement-mode transistor extends further than said gate electrode (59) of said depletion-mode transistor by a distance substantially equal to said total thickness of said third and fourth semiconductor layers (43, 44); and contact electrodes (51a, 51b, 51c) being formed on said first semiconductor layer (45) at both sides of each of the gate electrodes (58, 59).
Claim 11
Dependent Claim
51 words
A semiconductor device according to claim 8, wherein said first and third semiconductor layers are of a first composition, said second and fourth semiconductor layers and electron-supply layer are of a second composition, and said first composition has an etching rate substantially higher than the etching rate of the second composition.
Claim 12
Dependent Claim
41 words
A semiconductor device according to claim 9, wherein said substrate is of gallium-arsenide, said channel layer is of gallium-arsenide, said electron-supply layer and fourth and second semiconductor layers are of aluminum-gallium-arsenide, and said third and first semiconductor layers are of gallium-arsenide.
References Cited (Backward Citations)
US4163237A
Cited
US4635343A
Cited
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