Patent US6345496B1 successfully refreshed from Google Patents.
US6015993A
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Semiconductor diode with depleted polysilicon gate structure and method
Assignee: International Business Machines Corp
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Filing: 1998-08-31
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Granted: 2000-01-18
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Expires: 2018-08-31
Abstract
Abstract A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method mey be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.
Inventors
- 👤 Steven H. Voldman
- 👤 Robert J. Gauthier, Jr.
- 👤 Jeffrey S. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/201; H10D84/204; H10D84/212; H10D84/217; H10D12/00; H10D12/211; H10D8/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
155 words
A semiconductor chip comprising: a semiconductor layer including a first conduction region of a first conduction type and a second conduction region of a second conductivity type; a dielectric layer on said semiconductor layer; and a conducting layer on said dielectric layer between said first conduction region and said second conduction region, said conducting layer having a first region of a first conductivity type and a second region of a second conductivity type, said first region being electrically shorted to said second region, said first region being adjacent to said first conduction region and said second region being adjacent to said second conduction region, wherein at least one of said first and second conduction regions and said conducting layer is lightly doped or counter-doped such that a thickness of a depletion region in a respective one of said semiconductor layer and said conducting layer adjacent said dielectric layer increases in thickness with increasing electrical stress.
Claim 2
Dependent Claim
155 words
A semiconductor chip comprising: a semiconductor layer including a first conduction region of a first conduction type and a second conduction region of a second conductivity type; a dielectric layer on said semiconductor layer; and a conducting layer on said dielectric layer between said first conduction region and said second conduction region, said conducting layer having a first region of a first conductivity type and a second region of a second conductivity type, said first region being electrically shorted to said second region, said first region being adjacent to said first conduction region and said second region being adjacent to said second conduction region, wherein at least one of said first and second conduction regions and said conducting layer is lightly doped or counter-doped such that a thickness of a depletion region in a respective one of said semiconductor layer and said conducting layer adjacent said dielectric layer increases in thickness with increasing electrical stress.
Claim 3
Dependent Claim
17 words
The semiconductor chip of claim 1 further comprising a dielectric spacer on sidewalls of the conducting layer.
Claim 4
Dependent Claim
23 words
The semiconductor chip of claim 2 wherein said first conduction region and said second conduction region each have a trench along one side.
Claim 5
Dependent Claim
20 words
The semiconductor chip of claim 3 wherein the semiconductor layer is a silicon layer and the conducting layer is polysilicon.
Claim 6
Dependent Claim
14 words
The semiconductor chip of claim 4 wherein the silicon layer is a silicon wafer.
Claim 7
Dependent Claim
53 words
The semiconductor chip of claim 5 wherein said first conduction region and said second conduction region each include at least two doped regions, a first doped region of said at least two doped regions being doped to a dopant concentration lower than a second doped region of said at least two doped regions.
Claim 8
Dependent Claim
21 words
The semiconductor chip of claim 6 wherein said first doped region is between the second doped region and said polysilicon layer.
Claim 9
Dependent Claim
38 words
The semiconductor chip of claim 6 wherein at least two doped regions is three doped regions, said first doped region being doped to a dopant concentration lower than both of the other two of said three doped regions.
Claim 10
Dependent Claim
16 words
The semiconductor chip of claim 8 wherein said first doped region is between the other two.
Claim 11
Dependent Claim
15 words
The semiconductor chip of claim 4 wherein the silicon layer is on an insulating layer.
Claim 12
Dependent Claim
53 words
The semiconductor chip of claim 10 wherein said first conduction region and said second conduction region each include at least two doped regions, a first doped region of said at least two doped regions being doped to a dopant concentration lower than a second doped region of said at least two doped regions.
Claim 13
Dependent Claim
21 words
The semiconductor chip of claim 11 wherein said first doped region is between the second doped regions and said polysilicon layer.
Claim 14
Dependent Claim
38 words
The semiconductor chip of claim 11 wherein at least two doped regions is three doped regions, said first doped region being doped to a dopant concentration lower than both of the other two of said three doped regions.
Claim 15
Dependent Claim
16 words
The semiconductor chip of claim 13 wherein said first doped region is between the other two.
Claim 16
Dependent Claim
43 words
The semiconductor chip as recited in claim 1, wherein a dopant concentration in said at least one of said first and second conduction regions and said conducting layer is in the range of 10 14 /cm 2 to 10 15 /cm 2 .
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-01-17 | 2003-07-19 | 2004-01-18 | $2000.00 | Window Closed / Lapsed |
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