US4492974A
Expired / Lapsed
US
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DMOS With gate protection diode formed over base region
Assignee: Hitachi Ltd
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Filing: 1982-02-22
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Granted: 1985-01-08
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Expires: 2002-02-22
Abstract
Abstract A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n + -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n + -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.
Inventors
- 👤 Isao Yoshida
- 👤 Takeaki Okabe
- 👤 Mineo Katsueda
- 👤 Minoru Nagata
- 👤 Toshiaki Masuhara
- 👤 Kazutoshi Ashikawa
- 👤 Hideaki Kato
- 👤 Mitsuo Ito
- 👤 Shigeo Ohtaka
- 👤 Osamu Minato
- 👤 Yoshio Sakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/665; H10D8/00; H10D84/00; H10D84/101; H10D84/141; H10D84/148; H10D88/00; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
164 words
A semiconductor integrated circuit device comprising: a semiconductor body; a semiconductor element formed in said semiconductor body; a semiconductor region formed in a surface region of said semiconductor body and having an opposite conductivity type to that of said semiconductor body; and a protection element for protecting said semiconductor element, said protection element being formed in a semiconductor layer provided on an insulating film situated on said semiconductor region, said protection element including a pair of highly doped regions and a low doped region in such a manner that said low doped region is sandwiched between said highly doped regions and that a pn junction is formed between said low doped region and at least one of said highly doped regions, the number of impurity atoms per unit area at said low doped region being in a range from 10 13 to 10 15 cm -2 , and the thickness of said low doped region being in a range from 0.1 to 1 μm.
Claim 2
Dependent Claim
164 words
A semiconductor integrated circuit device comprising: a semiconductor body; a semiconductor element formed in said semiconductor body; a semiconductor region formed in a surface region of said semiconductor body and having an opposite conductivity type to that of said semiconductor body; and a protection element for protecting said semiconductor element, said protection element being formed in a semiconductor layer provided on an insulating film situated on said semiconductor region, said protection element including a pair of highly doped regions and a low doped region in such a manner that said low doped region is sandwiched between said highly doped regions and that a pn junction is formed between said low doped region and at least one of said highly doped regions, the number of impurity atoms per unit area at said low doped region being in a range from 10 13 to 10 15 cm -2 , and the thickness of said low doped region being in a range from 0.1 to 1 μm.
Claim 3
Dependent Claim
43 words
A semiconductor integrated circuit device according to claim 1, wherein said semiconductor element is an MOSFET, and the gate and the source of said MOSFET are connected to one of said highly doped regions and the other of said highly doped regions, respectively.
Claim 4
Dependent Claim
17 words
A semiconductor integrated circuit device according to claim 2, wherein said MOSFET is a vertical type MOSFET.
Claim 5
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 1, 2 or 3, wherein said highly doped regions are equal in conductivity type, and said low doped region is opposite in conductivity type to said highly doped regions.
Claim 6
Dependent Claim
42 words
A semiconductor integrated circuit device according to claim 1, 2 or 3, wherein said highly doped regions are opposite in conductivity type to each other, and said low doped region is equal in conductivity type to one of said highly doped regions.
Claim 7
Dependent Claim
20 words
A semiconductor integrated circuit device according to claim 1, wherein said semiconductor layer is made of a polycrystalline semiconductor material.
Claim 8
Dependent Claim
142 words
A semiconductor integrated circuit device comprising: a semiconductor body; a semiconductor element formed in said semiconductor body; a semiconductor region formed in a surface region of said semiconductor body and having an opposite conductivity type to that of said semiconductor body; and a protection element for protecting said semiconductor element, said protection element being formed in a semiconductor layer provided on an insulating film situated on said semiconductor region, said protection element including a pair of highly doped regions and a low doped region in such a manner that said low doped region is sandwiched between said highly doped regions and that a pn junction is formed between said low doped region and at least one of said highly doped regions, the impurity concentration of said low doped region being in a range from 10 17 to 10 19 cm -3 .
Claim 9
Dependent Claim
142 words
A semiconductor integrated circuit device comprising: a semiconductor body; a semiconductor element formed in said semiconductor body; a semiconductor region formed in a surface region of said semiconductor body and having an opposite conductivity type to that of said semiconductor body; and a protection element for protecting said semiconductor element, said protection element being formed in a semiconductor layer provided on an insulating film situated on said semiconductor region, said protection element including a pair of highly doped regions and a low doped region in such a manner that said low doped region is sandwiched between said highly doped regions and that a pn junction is formed between said low doped region and at least one of said highly doped regions, the impurity concentration of said low doped region being in a range from 10 17 to 10 19 cm -3 .
Claim 10
Dependent Claim
43 words
A semiconductor integrated circuit device according to claim 7, wherein said semiconductor element is an MOSFET, and the gate and the source of said MOSFET are connected to one of said highly doped regions and the other of said highly doped regions, respectively.
Claim 11
Dependent Claim
17 words
A semiconductor integrated circuit device according to claim 8, wherein said MOSFET is a vertical type MOSFET.
Claim 12
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 7, 8 or 9, wherein said highly doped regions are equal in conductivity type, and said low doped region is opposite in conductivity type to said highly doped regions.
Claim 13
Dependent Claim
42 words
A semiconductor integrated circuit device according to claim 7, 8 or 9, wherein said highly doped regions are opposite in conductivity type to each other, and said low doped region is equal in conductivity type to one of said highly doped regions.
Claim 14
Dependent Claim
20 words
A semiconductor integrated circuit device according to claim 7, wherein said semiconductor layer is made of a polycrystalline semiconductor material.
Claim 15
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 1 or 7, further comprising means for fixing said semiconductor region at a constant potential.
Claim 16
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 13, wherein said semiconductor region is fixed at ground potential.
Claim 17
Dependent Claim
38 words
A semiconductor integrated circuit device according to claim 1 or 7, wherein said semiconductor region is located in said semiconductor body relative to said protection element so that said entire protection element is formed over said semiconductor region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-08 | 1988-07-09 | 1989-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-08 | 1992-07-09 | 1993-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-08 | 1996-07-09 | 1997-01-08 | $7700.00 | Window Closed / Lapsed |