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US6011744A
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Programmable logic device with multi-port memory
Assignee: Cadence Design Systems Inc
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Filing: 1997-07-16
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Granted: 2000-01-04
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Expires: 2017-07-16
Abstract
Abstract An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
Inventors
- 👤 Stephen P. Sample
- 👤 Michael R. Butts
- 👤 Kevin A. Norman
- 👤 Rakesh H. Patel
- 👤 Chao Chiang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/17772; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/1075; G11C7/22; G11C8/00; G11C8/16; H03K19/17724; H03K19/17728; H03K19/17736; H03K19/1776; H03K19/17764; H03K19/1778
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
97 words
An integrated circuit comprising: a memory including at least one memory block; said memory block having memory cells, said memory block having a configurable width and a configurable depth such that increasing the width results in decreasing the depth and decreasing the width results in increasing the depth; wherein said memory block further comprises a read port that reads data out of said memory block and a write port that writes data into said memory block where the width and depth of said read port is independently configurable of the width and depth of said write port.
Claim 2
Dependent Claim
97 words
An integrated circuit comprising: a memory including at least one memory block; said memory block having memory cells, said memory block having a configurable width and a configurable depth such that increasing the width results in decreasing the depth and decreasing the width results in increasing the depth; wherein said memory block further comprises a read port that reads data out of said memory block and a write port that writes data into said memory block where the width and depth of said read port is independently configurable of the width and depth of said write port.
Claim 3
Dependent Claim
50 words
The integrated circuit of claim 1 wherein said memory block comprises a plurality of read ports that read data out of said memory block where the width and depth of one of said read ports is independently configurable of the width and depth of the remaining of said read ports.
Claim 4
Dependent Claim
50 words
The integrated circuit of claim 1 wherein said memory block further comprises a plurality of write ports that write data into said memory block wherein the width and depth of one of said write ports is independently configurable of the width and depth of the remaining of said write ports.
Claim 5
Dependent Claim
48 words
The integrated circuit of claim 1 wherein said integrated circuit further comprises: a plurality of logic blocks which transmit and receive signals; an interconnect network to route the signals between said logic blocks where said memory is associated with said logic blocks and stores certain of the signals.
Claim 6
Dependent Claim
54 words
The integrated circuit of claim 4, said memory block further comprising a read port that reads data out of said memory block and a write port that writes data into said memory block wherein the width and depth of said read port is independently configurable of the width and depth of said write port.
Claim 7
Dependent Claim
50 words
The integrated circuit of claim 4, said memory block further comprising a plurality of read ports that read data out of said memory block wherein the width and depth of one of said read ports is independently configurable of the width and depth of the remaining of said read ports.
Claim 8
Dependent Claim
49 words
The integrated circuit of claim 4, said memory block further comprising a plurality of write ports that write data into said memory block wherein the width and depth of one of said write ports is independently configurable of the width and depth of the remaining of said write ports.
Claim 9
Dependent Claim
51 words
The integrated circuit of claim 1 further comprising: said memory receiving data signals; said memory cells within said memory block being configured in rows and columns; and write buffer circuitry selectively routing each data signal received by said memory to a said memory cell of a column of said memory block.
Claim 10
Dependent Claim
52 words
The integrated circuit of claim 1 further comprising: said memory storing data signals; said memory cells within said memory block being configured in rows and columns; and read buffer circuitry selectively routing each data signal from a said memory cell of a column of said memory block out of said memory block.
Claim 11
Dependent Claim
76 words
The integrated circuit of claim 1 further comprising: said memory storing data signals; said memory cells within said memory block being configured in rows and columns; write buffer circuitry selectively routing each data signal received by said memory to a said memory cell of a column of said memory block; and read buffer circuitry selectively routing each data signal from a said memory cell of a column of said memory block out of said memory block.
Claim 12
Dependent Claim
32 words
The integrated circuit of claim 1 wherein said memory block is configurable to act as one eight-bit wide memory, two four-bit wide memories, four two-bit wide memories, or eight one-bit wide memories.
References Cited (Backward Citations)
US34444A
Cited
US4293783A
Cited
EP0081917A1
Cited
EP0225715A2
Cited
US5042004A
Cited
US4893280A
Cited
US4825414A
Cited
US4855958A
Cited
JPH0191526A
Cited
JPH0191525A
Cited
US4963770A
Cited
USRE34444E
Cited
US5212666A
Cited
EP0410759A2
Cited
US5343406A
Cited
EP0415542A2
Cited
US5329460A
Cited
US4975601A
Cited
EP0420389A1
Cited
US5276842A
Cited
US5122685A
Cited
US5313119A
Cited
EP0507507A2
Cited
US5412260A
Cited
US5550782A
Cited
US5668771A
Cited
EP0530985A2
Cited
US5231312A
Cited
EP0569137A2
Cited
US5384500A
Cited
US5329493A
Cited
WO1994010754A1
Cited
US5414377A
Cited
US5408434A
Cited
US5386155A
Cited
US5809281A
Cited
US5596742A
Cited
US5352940A
Cited
US5315178A
Cited
US5375089A
Cited
US5530670A
Cited
WO1995015152A1
Cited
US5835405A
Cited
US5426378A
Cited
US5566123A
Cited
US5572148A
Cited
US5852608A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-01-03 | 2003-07-05 | 2004-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-03 | 2007-07-05 | 2008-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-03 | 2011-07-05 | 2012-01-04 | $7700.00 | Window Closed / Lapsed |