US5212666A
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Memory apparatus having flexibly designed memory capacity
Assignee: Seiko Epson Corp
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Filing: 1990-07-10
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Granted: 1993-05-18
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Expires: 2010-07-10
Abstract
Abstract A memory apparatus has a W(1+J/N) (words)×D (bits) configuration employing (N+J) semiconductor memory units having (N+J) W (words)×B (bits) semiconductor memory elements wherein N=D/B=2 d-b and J is a positive integer wherein J<N; W=2 w and w is a positive integer; and B=2 b where b is zero or a positive integer satisfying b<d. For example, five 256K×4 1M DRAMs are employed so that four out of five DRAMs always correspond to access from a microprocessor. Furthermore, a 640-Kbyte memory address space is equally divided into five 128-Kbyte memory address areas and the correspondence between the 128-Kbyte memory address areas and four out of the five DRAMs is regularly determined in turn, thereby constituting a 640-Kbyte memory apparatus (320 Kwords×16 bits) employing only 1M DRAMs. More particularly, a memory capacity can be set in relatively small units, i.e., in units of W·J/N words×D bits by employing only semiconductor memory units of a single type.
Inventors
- 👤 Koji Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:05
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
75 words
A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words×D bits, the memory apparatus comprising: (N+J) memory units, each having a W words×B bits configuration; and wherein D=2 d , and d is a positive integer, W=2 w , and w is a positive integer, B=2 b , b is zero or a positive integer and b<d, J is a positive integer and J<N, and N=D/B=2 d-b .
Claim 2
Dependent Claim
75 words
A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words×D bits, the memory apparatus comprising: (N+J) memory units, each having a W words×B bits configuration; and wherein D=2 d , and d is a positive integer, W=2 w , and w is a positive integer, B=2 b , b is zero or a positive integer and b<d, J is a positive integer and J<N, and N=D/B=2 d-b .
Claim 3
Dependent Claim
153 words
A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words×D bits, the memory apparatus comprising: (N+J) memory units, each having a W words×B bits configuration and being equally divided into P element address areas, a 1 , a 2 , . . . , a p ; wherein D=2 d , and d is a positive integer, W=2 w , and w is a positive integer, B=2 b , b is zero or a positive integer and b<d, J is a positive integer and J<N, N=D/B=2 d-b , and P=N·L/J and P and L are positive integers; and wherein said W(1+J/N) words×D bits memory configuration is divided into (P+L) memory address areas A 1 , A 2 , . . . , A P+L , so that each memory address area comprises N element address areas, only one of which comes from a corresponding memory unit.
Claim 4
Dependent Claim
153 words
A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words×D bits, the memory apparatus comprising: (N+J) memory units, each having a W words×B bits configuration and being equally divided into P element address areas, a 1 , a 2 , . . . , a p ; wherein D=2 d , and d is a positive integer, W=2 w , and w is a positive integer, B=2 b , b is zero or a positive integer and b<d, J is a positive integer and J<N, N=D/B=2 d-b , and P=N·L/J and P and L are positive integers; and wherein said W(1+J/N) words×D bits memory configuration is divided into (P+L) memory address areas A 1 , A 2 , . . . , A P+L , so that each memory address area comprises N element address areas, only one of which comes from a corresponding memory unit.
Claim 5
Dependent Claim
49 words
A memory apparatus according to claim 1 or 2 wherein N memory units are designated and said D-bit data bus is divided into N sections each being B-bit wide, and wherein each of said N designated memory units corresponds to one of said N sections without overlapping each other.
Claim 6
Dependent Claim
80 words
A memory apparatus according to claim 3, further comprising a plurality of bidirectional buffers controllable by switching between their respective ON/OFF states and between their respective directions of data flow and wherein each of the remaining J memory units not included in said N designated memory units is coupled to selected ones of said N sections of said D-bit data bus through said bidirectional buffers so as to organize the memory apparatus into said memory configuration of W(1+J/N) words×D bits.
Claim 7
Dependent Claim
21 words
A memory apparatus according to claim 2, further comprising means for coupling to another memory apparatus having a D-bit data bus.
Claim 8
Dependent Claim
26 words
A memory apparatus according to claim 2 wherein D=16, d=4, W=256K, w=18, B=4, b=2, N=4, n=2, J=1, L=1, P=4, and said memory configuration has 640 Kbytes.
Claim 9
Dependent Claim
199 words
A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words×D bits, the memory apparatus comprising: (N+J) commercially available semiconductor memory units each having a W words×B bits configuration and wherein D>B and N is a fixed number representative of a number of memory units necessary for achieving a configuration having a data bus of D-bit wide and J is a flexible number less than N and representative of an additional number of memory units necessary for achieving said memory configuration of W(1+J/N) words×D bits; wherein each memory unit is divided into P memory element address areas, a 1 , a 2 , . . . , a p , each having W/P words, wherein P=N·L/J, L is a flexible number; and wherein said W(1+J/N) words×D bits memory configuration is divided into (P+L) memory address areas A 1 , A 2 , . . . , A P+L , so that each memory address area comprises an addressable set of N element address areas, only one of which comes from a corresponding memory unit, wherein L represents an additional number of memory address areas in said memory configuration attributable to J memory units.
Claim 10
Dependent Claim
199 words
A memory apparatus having a data bus of D-bit wide and a memory configuration of W(1+J/N) words×D bits, the memory apparatus comprising: (N+J) commercially available semiconductor memory units each having a W words×B bits configuration and wherein D>B and N is a fixed number representative of a number of memory units necessary for achieving a configuration having a data bus of D-bit wide and J is a flexible number less than N and representative of an additional number of memory units necessary for achieving said memory configuration of W(1+J/N) words×D bits; wherein each memory unit is divided into P memory element address areas, a 1 , a 2 , . . . , a p , each having W/P words, wherein P=N·L/J, L is a flexible number; and wherein said W(1+J/N) words×D bits memory configuration is divided into (P+L) memory address areas A 1 , A 2 , . . . , A P+L , so that each memory address area comprises an addressable set of N element address areas, only one of which comes from a corresponding memory unit, wherein L represents an additional number of memory address areas in said memory configuration attributable to J memory units.
Claim 11
Dependent Claim
18 words
A memory apparatus according to claim 2, wherein said (N+J) memory units are commercially available semiconductor memory units.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-17 | 1996-11-16 | 1997-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-17 | 2000-11-16 | 2001-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-17 | 2004-11-16 | 2005-05-18 | $7700.00 | Window Closed / Lapsed |