Programmable input/output cell

Claim 2

A programmable input/output cell, responsive to a data signal generated by a portion of an integrated circuit, and a plurality of dynamic control signals, for configuring an input/output port of said integrated circuit, comprising: input select multiplexer means, responsive to a programmable input select signal, receiving said data signal and a signal received via said input/output port for selectively coupling one of said received signals to an input multiplexer output in response to said input select signal; register/latch means, having a programmable fusible link, connected to the output of said input select multiplexer means and responsive to a clock/latch enable signal selectably operable in either a register or a latch mode, in response to the status of said register/latch fusible link, for registering or latching said signal received from said input select multiplexer and for generating therefrom at a register/latch output a registered or latched signal; output select multiplexer means, responsive to a programmable output select signal, responsive to a first of said dynamic control signals, and receiving said data signal and said signal generated by said register/latch means for selectively coupling one of said received signals, or its complemented signal, to an output multiplexer output in response to said output select signal and to said first dynamic control signal; and input/output means receiving said signal generated at said output of said output select multiplexer means for generating therefrom a signal at said integrated circuit input/output port and for receiving a signal received at said input/output port.

Claim 3

An input/output cell according to claim 1, further including: clock select multiplexer means, having a first programmable fusible link, receiving a clock signal and a second of said dynamic control signals for selectively coupling one of said received signals to an output of said clock select multiplexer means in response to the status of said first clock select multiplexer fusible link, said signal so-coupled being said clock/latch enable signal received by said register/latch means.

Claim 4

An input/output cell according to claim 2, wherein said clock select multiplexer means further includes a second programmable fusible link, said clock select multiplexer means further for selectively generating said clock/latch enable signal received by said register/latch means in a true or a reverse polarity, in response to the status of said second clock fusible link.

Claim 5

An input/output cell according to claim 2, further including: feedback multiplexer means, responsive to a programmable feedback select signal, receiving said data signal and said signal generated by said register/latch means for selectively coupling one of said received signals to a feedback multiplexer means output in response to said feedback select signal, wherein said signal so-coupled is conducted to said portion of said integrated circuit portion.

Claim 6

An input/output cell according to claim 1, wherein said input/output means is responsive to an output enable control signal and an output enable polarity control signal, said input/output means further selectively enabling generation of said signal at said input/output port or disabling generation of said signal, in response to said output enable control signal, said input/output cell further including: output enable multiplexer selection means, responsive to a programmable output enable control signal and an output enable polarity control signal, connected to said input/output means, receiving a third and a fourth dynamic control signals for selectively generating said third or said fourth dynamic control signal received by said input/output means in a true or a reverse polarity, in response to said output enable and said output polarity control signals.

Claim 7

An input/output cell according to claim 1, wherein said register/latch means is further responsive to a fifth of said dynamic control signals for asynchronous resetting of said registered or latched signal generated thereby to a predetermined level, in response to said fifth dynamic control signal, said input/output cell further including: asynchronous reset polarity selection means, responsive to a programmable asynchronous reset polarity selection signal, connected to said register/latch means, receiving said fifth dynamic control signal for selectively generating said fifth dynamic control signal received by said input/output means in a true or a reverse polarity, in response to said asynchronous reset polarity control signal.

Claim 8

An input/output cell according to claim 6, wherein said register/latch means is further responsive to a sixth of said dynamic control signals for asynchronous presetting of said registered or latched signal generated thereby to a predetermined level, in response to said sixth dynamic control signal, said input/output cell further including: asynchronous preset polarity selection means, responsive to a programmable asynchronous preset polarity selection signal, connected to said register/latch means, receiving said sixth dynamic control signal for selectively generating said sixth dynamic control signal received by said input/output means in a true or a reverse polarity, in response to said asynchronous polarity control signal.

Claim 9

An input/output cell according to claim 5, further including: means responsive to said signal generated by said input/output means for generating signals to said portion of said integrated circuit portion.

Claim 10

An input/output cell according to claim 1 further including input multiplexer preload means responsive to a seventh and an eighth dynamic control signal for generating said input select control signal received by said input select multiplexer.

Claim 11

An input/output cell according to claim 1 where the source of predetermined ones of said dynamic control signals is selectable from an external pin, or from said portion, of said integrated circuit.

Claim 12

An input/output cell according to claim 1 wherein said input select multiplexer means includes a programmable fusible link the status of which determines said input select signal.

Claim 13

An input/output cell according to claim 1 wherein said output select multiplexer includes a first and a second programmable fusible link the status of which determines said output select signal.

Claim 14

An input/output cell according to claim 4 wherein said feedback multiplexer means includes a programmable fusible link the status of which determines said feedback select signal.

Claim 15

An input/output cell according to claim 5 wherein said output enable multiplexer selection means includes a first and a second programmable fusible link the status of which determines said output enable and said output enable polarity signals, respectively.

Claim 16

An input/output cell according to claim 6 wherein said asynchronous reset polarity selection means is an exclusive OR gate receiving at a first input terminal said fifth dynamic control signal and at a second input terminal said asynchronous reset polarity control signal.

Claim 17

An input/output cell according to claim 7 wherein said asynchronous preset polarity selection means is said an exclusive OR gate receiving at a first input terminal said sixth dynamic control signal and at a second input terminal said asynchronous preset polarity control signal.

Claim 18

An input/output cell according to claim 6 wherein said asynchronous reset polarity selection means includes a programmable fusible link the status of which determines said asynchronous reset polarity control signal.

Claim 19

An input/output cell according to claim 7 wherein said asynchronous preset polarity selection means includes a programmable fusible link the status of which determines said asynchronous preset polarity control signal.

Claim 20

An input/output cell according to claim 1 wherein said input select control signal is generated by a memory cell.

Claim 21

An input/output cell according to claim 1 wherein said output select control signal is generated by a memory cell.

Claim 22

An input/output cell according to claim 4 wherein said feedback select signal is generated by a memory cell.

Claim 23

An input/output cell according to claim 5 wherein said output enable and said output enable polarity signals are generated by a memory cell.

Claim 24

An input/output cell according to claim 6 wherein said asynchronous reset polarity control signal is generated by a memory cell.

Claim 25

An input/output cell according to claim 7 wherein said asynchronous preset polarity control signal is generated by a memory cell.

Claim 26

An input/output cell according to claim 9 wherein said input multiplexer preload means includes a programmable fusible link and an OR gate receiving said seventh and eighth dynamic control signals at a first and a second input terminal, respectively, and connected to said programmable fusible link at a third input terminal, for generating said input select signal, and wherein said seventh dynamic control signal is conducted from an external pin, and said eighth dynamic control signal is received from said portion of said integrated circuit.

Claim 27

In a programmable array logic device contained on an integrated circuit chip having a portion comprising a plurality of logic cell means dynamically generating logic signals, and a second plurality of combinatorial logic means for combining a subset of logic signals to generate a plurality of combinatorial signals therefrom, a programmable input/output cell, responsive to a data signal, being a predetermined one of said combinatorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit, for configuring an input/output port of said integrated circuit, comprising: input select multiplexer means, responsive to a programmable input select signal, receiving said data signal and a signal received via said input/output port for selectively coupling one of said received signals to an input multiplexer output in response to said input select signal; register/latch means, having a programmable fusible link, connected to the output of said input select multiplexer means and responsive to a clock/latch enable signal selectably operable in either a register or a latch mode, in response to the status of said register/latch fusible link, for registering or latching said signal received from said input select multiplexer and for generating therefrom at a register/latch output a registered or latched signal; output select multiplexer means, responsive to a programmable output select signal, responsive to a first of said dynamic control signals, and receiving said data signal and said signal generated by said register/latch means for selectively coupling one of said received signals, or its complemented signal, to an output multiplexer output in response to said output select signal and to said first dynamic control signal; and input/output means receiving said signal generated at said output of said output select multiplexer means for generating therefrom a signal at said integrated circuit input/output port and for receiving a signal received at said input/output port.

Claim 28

In a programmable array logic device contained on an integrated circuit chip having a portion comprising a plurality of logic cell means dynamically generating logic signals, and a second plurality of combinatorial logic means for combining a subset of logic signals to generate a plurality of combinatorial signals therefrom, a programmable input/output cell, responsive to a data signal, being a predetermined one of said combinatorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit, for configuring an input/output port of said integrated circuit, comprising: input select multiplexer means, responsive to a programmable input select signal, receiving said data signal and a signal received via said input/output port for selectively coupling one of said received signals to an input multiplexer output in response to said input select signal; register/latch means, having a programmable fusible link, connected to the output of said input select multiplexer means and responsive to a clock/latch enable signal selectably operable in either a register or a latch mode, in response to the status of said register/latch fusible link, for registering or latching said signal received from said input select multiplexer and for generating therefrom at a register/latch output a registered or latched signal; output select multiplexer means, responsive to a programmable output select signal, responsive to a first of said dynamic control signals, and receiving said data signal and said signal generated by said register/latch means for selectively coupling one of said received signals, or its complemented signal, to an output multiplexer output in response to said output select signal and to said first dynamic control signal; and input/output means receiving said signal generated at said output of said output select multiplexer means for generating therefrom a signal at said integrated circuit input/output port and for receiving a signal received at said input/output port.

Claim 29

27 . In a programmable array logic device contained on an integrated circuit chip having a portion comprising a plurality of logic cell means dynamically generating logic signals, and a second plurality of combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom, a first and a second plurality of programmable input/output cells, each cell of said first, said second, plurality responsive to a first, a second, clock/latch enable signal, respectively, a data signal, being a predetermined one of said combinatorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for configuring a first, a second, plurality, respectively, of input/output ports of said integrated circuit.

Claim 30

27 . In a programmable array logic device contained on an integrated circuit chip having a portion comprising a plurality of logic cell means dynamically generating logic signals, and a second plurality of combinatorial logic means for combining a subset of logic signals and for generating a plurality of combinatorial signals therefrom, a first and a second plurality of programmable input/output cells, each cell of said first, said second, plurality responsive to a first, a second, clock/latch enable signal, respectively, a data signal, being a predetermined one of said combinatorial signals, and a plurality of dynamic control signals, selectable from signals applied to an external pin of said integrated circuit chip and predetermined ones of said plurality of combinatorial signals generated by said portion of said integrated circuit for configuring a first, a second, plurality, respectively, of input/output ports of said integrated circuit.

Claim 31

A programmable array logic device according to claim 27 wherein said device receives a first and a second bank clock signal, said first plurality of input/ouput cells receiving said first bank clock signal as its clock/latch enable signal, said device further including: bank clock select multiplexer means, having a programmable fusible link, receiving said first and said second bank clock signals for selectively coupling one of said received signals to an output of said bank clock select multiplexer means in response to the status of said bank clock select multiplexer fusible link, said signal so-coupled being said clock/latch enable signal received by said second plurality of input/output cells.