Semiconductor memory device and control method for the same

Claim 2

A semiconductor memory device comprising a single write bus, k read buses, where k is an integer greater than one (1), a memory cell array section including a plurality of bit-line pairs partitioned into groups of k bit-line pairs, a plurality of write registers for receiving data from said write bus, and sets of read registers, said sets respectively corresponding to said read buses, wherein said semiconductor memory device comprises: a first write data-transfer means for transferring data from said write registers to every first bit-line pair of said bit-line pair groups of said memory cell array section; second, . . . , kth write data-transfer means for transferring data from said write registers to every (i+1)th bit-line pair of said bit-line pair groups (where i=1, 2, . . . , k-1) of said memory cell array section; a first read data-transfer means which is capable of transferring the data from said every first bit-line pair of the bit-line pair groups of said memory cell array section to said sets of read registers; and second, . . . , kth read data-transfer means which are capable of transferring the data from said every (i+1)th bit-line pair of the bit-line pair groups of said memory cell array section to said sets of read registers.

Claim 3

A control method for the semiconductor memory device of claim 1, wherein data are sequentially input from the single write bus to the write registers, and then the thus input data are transferred to said every first bit-line pair of the bit-line pair groups of the memory cell array section by the first write data-transfer means, and thereafter, data are again sequentially input from said write bus to the write registers, and the thus input data are transferred to said every (i+1)th bit-line pair of said bit-line pair groups of said memory cell array section sequentially by the (i+1)th write data-transfer means, said inputting and transfer of data being repeated, thereby completing the writing of the data into all the bit-line pairs of said memory cell array section; and thereafter, the data in said every first bit-line pair of said bit-line pair groups of said memory cell array section are transferred by the first read data-transfer means into a single set of read registers corresponding to one of the read buses which is used for reading of data, and accordingly, the thus transferred data are sequentially read out of said read bus, and then the data in said every (i+1)th bit-line pair of the bit-line pair groups of said memory cell array section are transferred into said single set of read registers sequentially by the (i+1)th read data-transfer means, and accordingly, the thus transferred data are sequentially read out of said read bus, said transfer and reading of data being repeated, thereby completing the reading of the data from all the bit-line pairs of said memory cell array section.

Claim 4

A semiconductor memory device comprising a single write bus, k read buses, where k is an integer greater than one (1), a memory cell array section including a plurality of bit-line pairs partitioned into groups of k bit-line pairs, a plurality of write registers for receiving data from said write bus, said write registers partitioned into groups of k write registers, and sets of read registers, said sets respectively corresponding to said read buses, wherein said write registers are respectively connected to the bit-line pairs of said memory cell array section, and said semiconductor memory device comprises: a first data-write means for transferring data from said write bus to every first write register of said write register groups; second, . . . , kth data-write means for transferring data from said write bus to every (i+1)th write register of said write register groups (where i=1, 2, . . . , k-1); a first read data-transfer means which is capable of transferring data from every first bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers; and second, . . . , kth read data-transfer means which are capable of transferring data from every (i+1)th bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers.

Claim 5

A semiconductor memory device comprising a single write bus, k read buses, where k is an integer greater than one (1), a memory cell array section including a plurality of bit-line pairs partitioned into groups of k bit-line pairs, a plurality of write registers for receiving data from said write bus, said write registers partitioned into groups of k write registers, and sets of read registers, said sets respectively corresponding to said read buses, wherein said write registers are respectively connected to the bit-line pairs of said memory cell array section, and said semiconductor memory device comprises: a first data-write means for transferring data from said write bus to every first write register of said write register groups; second, . . . , kth data-write means for transferring data from said write bus to every (i+1)th write register of said write register groups (where i=1, 2, . . . , k-1); a first read data-transfer means which is capable of transferring data from every first bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers; and second, . . . , kth read data-transfer means which are capable of transferring data from every (i+1)th bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers.

Claim 6

A control method for the semiconductor memory device of claim 3, wherein data are sequentially input from the single write bus to said every first write register of said write register groups by the first data-write means, and then data sequentially input to said write bus are input to said every (i+1)th write register of said write register groups repeatedly by the (i+1)th data-write means, and thereafter, the data thus input to the write registers are respectively written to the bit-line pairs of the memory cell array section; and thereafter, the data in said every first bit-line pair of said bit-line pair groups of said memory cell array section are transferred by the first read data-transfer means into a single set of read registers corresponding to one of the read buses which is used for reading of data, and accordingly, the thus transferred data are sequentially read out of said read bus, and then the data in said every (i+1)th bit-line pair of said bit-line pair groups of said memory cell array section are transferred into said single set of read registers sequentially by the (i+1)th read data-transfer means, and accordingly, the thus transferred data are sequentially read out of said read bus, said transfer and reading of data being repeated, thereby completing the reading of the data from all the bit-line pairs of said memory cell array section.

Claim 7

The semiconductor memory device of claims 1 or 3, or the control method of claims 2 or 4, wherein the integer k is 2.

Claim 8

A semiconductor memory device comprising: a single write bus; k read buses, where k is an integer greater than zero (0); a memory cell array section including a plurality of bit-line pairs partitioned into groups of k bit-line pairs; a plurality of write registers for receiving data from said write bus, said write registers partitioned into groups of k write registers; sets of read registers, said sets respectively corresponding to said k read buses; and line registers for receiving data from said write bus and outputting the data to said k read buses, wherein said write registers are respectively connected to the bit-line pairs of said memory cell array section, and said semiconductor memory device comprises; a first data-write means for transferring data from said write bus to every first write register of said write register groups; second, . . . , kth data-write means for transferring data from said write bus to every (i+1)th write register of said write register groups (where i=2, . . . , k); a first read data-transfer means which is capable of transferring data from every first bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers; and second, . . . , kth read data-transfer means which are capable of transferring data from every (i+1)th bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers.

Claim 9

A semiconductor memory device comprising: a single write bus; k read buses, where k is an integer greater than zero (0); a memory cell array section including a plurality of bit-line pairs partitioned into groups of k bit-line pairs; a plurality of write registers for receiving data from said write bus, said write registers partitioned into groups of k write registers; sets of read registers, said sets respectively corresponding to said k read buses; and line registers for receiving data from said write bus and outputting the data to said k read buses, wherein said write registers are respectively connected to the bit-line pairs of said memory cell array section, and said semiconductor memory device comprises; a first data-write means for transferring data from said write bus to every first write register of said write register groups; second, . . . , kth data-write means for transferring data from said write bus to every (i+1)th write register of said write register groups (where i=2, . . . , k); a first read data-transfer means which is capable of transferring data from every first bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers; and second, . . . , kth read data-transfer means which are capable of transferring data from every (i+1)th bit-line pair of said bit-line pair groups of said memory cell array section to said sets of read registers.

Claim 10

A control method for the semiconductor memory device of claim 6, wherein data are first sequentially input from the single write bus to the line registers, and then data sequentially input to said write bus are input to said every first write register of said write register groups by the first data-write means, and then data sequentially input to said write bus are input to said every (i+1)th write register of said write register groups repeatedly by the (i+1)th data-write means, and thereafter, the data thus input to the write registers are respectively written to the bit-line pairs of the memory cell array section; and thereafter, while the data in said line registers are being sequentially read out into one of the read buses which is used for reading of data, the data in said every first bit-line pair of said bit-line pair groups of said memory cell array section are transferred by the first read data-transfer means into a single set of read registers corresponding to said read bus, and accordingly, the thus transferred data are sequentially read out of said read bus, and then the data in said every (i+1)th bit-line pair of said bit-line pair groups of said memory cell array section are transferred into said single set of read registers sequentially by the (i+1)th read data-transfer means, and accordingly, the thus transferred data are sequentially read out of said read bus, said transfer and reading of data being repeated, thereby completing the reading of the data from all the bit-line pairs of said memory cell array section.

Claim 11

The semiconductor memory device of claim 6, or the control method of claim 7, wherein the integer k is one (1).