Memory device that functions as a content addressable memory or a random access memory

Claim 1

A programmable logic device comprising a plurality of logic circuits interconnected through an interconnection network, each logic circuit comprising: an array of memory cells, each memory cell being (a) responsive to an address signal at the location of that cell to output data stored in the cell, and (b) operable to compare data input to it with data stored in it and to output a match signal when said input data matches said stored data; first circuitry for operating said array as a random access memory (RAM) with the cells in mode a); second circuitry for operating said array as a content addressable memory (CAM) with the cells in mode b); and a mode select circuit operable to selectively control operation of the cell as CAM or RAM, the logic device further comprising programming circuitry arranged to control the state of the mode select circuits.