EP0569137A2
Expired / Lapsed
EP
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Programmable logic array integrated circuit
Assignee: Altera Corp
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Filing: 1993-04-07
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Granted: —
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Expires: 2013-04-07
Abstract
Abstract A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.
Inventors
- 👤 Richard G. Cliff
- 👤 Craig Schilling Lytle
- 👤 Bahram Ahanin
- 👤 Francis B. Heile
- 👤 Bruce B. Pedersen
- 👤 Kerry Veenstra
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 15:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704; H03K19/17724; H03K19/17728; H03K19/1774; H03K19/1778; H03K19/17792
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
379 words
A programmable logic array integrated circuit (10) including a plurality of logic modules (12), each of which has a plurality of inputs (A-D) and at least one output (54) for producing as said output a programmable logical function of said inputs, said logic modules being grouped in a plurality of logic array blocks (14), said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks; a plurality of first conductors (26) associated with each of said blocks for selectively applying the outputs of the logic modules in the associated block to the inputs of the logic modules in that block; a plurality of second conductors (20) extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each of which groups is associated with a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the associated row; a plurality of third conductors (22) extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each of which groups is associated with a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the associated column; means (56, 57, 58, 60) for selectively applying the output of each logic module to at least one of the second or third conductors in the group of second or third conductors associated with the block which includes that logic module; and means (58, 60) for selectively connecting each of said second conductors to at least one of said third conductors, characterized by a plurality of fourth conductors (24) associated with each of said blocks; means (50) for selectively connecting to each of the fourth conductors associated with each of said blocks any one of a multiplicity of said second or third conductors in the group of second or third conductors associated with that block; and means (52) for selectively connecting each of said fourth conductors associated with each of said blocks to the inputs of the logic modules in that block.
Claim 2
Dependent Claim
379 words
A programmable logic array integrated circuit (10) including a plurality of logic modules (12), each of which has a plurality of inputs (A-D) and at least one output (54) for producing as said output a programmable logical function of said inputs, said logic modules being grouped in a plurality of logic array blocks (14), said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks; a plurality of first conductors (26) associated with each of said blocks for selectively applying the outputs of the logic modules in the associated block to the inputs of the logic modules in that block; a plurality of second conductors (20) extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each of which groups is associated with a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the associated row; a plurality of third conductors (22) extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each of which groups is associated with a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the associated column; means (56, 57, 58, 60) for selectively applying the output of each logic module to at least one of the second or third conductors in the group of second or third conductors associated with the block which includes that logic module; and means (58, 60) for selectively connecting each of said second conductors to at least one of said third conductors, characterized by a plurality of fourth conductors (24) associated with each of said blocks; means (50) for selectively connecting to each of the fourth conductors associated with each of said blocks any one of a multiplicity of said second or third conductors in the group of second or third conductors associated with that block; and means (52) for selectively connecting each of said fourth conductors associated with each of said blocks to the inputs of the logic modules in that block.
Claim 3
Dependent Claim
110 words
The apparatus defined in claim 1 further characterized in that said means (50) for selectively connecting to each of the fourth conductors associated with each of said blocks any one of a multiplicity of said second or third conductors comprises a first programmable logic connector (50) connected between said fourth conductor and said multiplicity of said second or third conductors; and programmable function control element means (51) for controlling each first programmable logic connector to select at least one of the second or third conductors connected to that first programmable logic connector as a source for a signal applied to the fourth conductor connected to that first programmable logic connector.
Claim 4
Dependent Claim
107 words
The apparatus defined in claim 2 further characterized in that said means (52) for selectively connecting each of said fourth conductors associated with each of said blocks to the inputs of the logic modules in that block comprises a second programmable logic connector connected (52) between a multiplicity of said fourth conductors and each input of said logic modules; and programmable function control element means for controlling said second programmable logic connector to select at least one of the fourth conductors connected to that second programmable logic connector as a source for a signal applied to the logic module input connected to that second programmable logic connector.
Claim 5
Dependent Claim
46 words
The apparatus defined in claim 3 further characterized in that each second programmable logic connector (52) is additionally connected between a multiplicity of the first conductors (26) associated with the same block that the fourth conductors connected to that second programmable logic connector are associated with.
Claim 6
Dependent Claim
65 words
The apparatus defined in claim 4 further characterized in that said programmable function control element for controlling each second programmable logic connector causes that second programmable logic connector to select at least one of the first and fourth conductors connected to that second programmable logic connector as a source for a signal applied to the logic module input connected to that second programmable logic connector.
Claim 7
Dependent Claim
68 words
The apparatus defined in claim 1 further characterized by first and second clock signal conductors (30, 32, 36) for respectively conveying first and second clock signals (CLK1, CLK2) to substantially every one of said logic modules (12); and means (120) associated with each of said logic modules for selecting the clock signal on one of said first and second clock signal conductors for application to said logic module.
Claim 8
Dependent Claim
132 words
A programmable logic array integrated circuit (10) including a plurality of programmable logic modules (12), each of which has a plurality of inputs (A-D) and at least one output (54) for producing as said output a programmable logical function of said inputs; and a network of interconnection conductors (20, 22, 24, 26) for programmably connecting the output of substantially any of said logic modules to substantially any of said logic module inputs, characterized by first and second clock signal conductors (30, 32, 36) for respectively conveying first and second clock signals (CLK1, CLK2) to substantially every one of said logic modules; and means (120) associated with each of said logic modules for selecting the clock signal on one of said first and second clock signal conductors for application to said logic module.
Claim 9
Dependent Claim
132 words
A programmable logic array integrated circuit (10) including a plurality of programmable logic modules (12), each of which has a plurality of inputs (A-D) and at least one output (54) for producing as said output a programmable logical function of said inputs; and a network of interconnection conductors (20, 22, 24, 26) for programmably connecting the output of substantially any of said logic modules to substantially any of said logic module inputs, characterized by first and second clock signal conductors (30, 32, 36) for respectively conveying first and second clock signals (CLK1, CLK2) to substantially every one of said logic modules; and means (120) associated with each of said logic modules for selecting the clock signal on one of said first and second clock signal conductors for application to said logic module.
Claim 10
Dependent Claim
201 words
A programmable logic array integrated circuit comprising: a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being disposed on said circuit in a two dimensional array; a plurality of first conductors extending substantially parallel to a first dimension of said array; a plurality of second conductors extending substantially parallel to a second dimension of said array; an input pin associated with each of said first conductors; first tri-state driver means associated with each of said first conductors, each of said first tri-state driver means being programmable to selectively apply to the associated first conductor a signal applied to the input pin associated with that first conductor; a programmable switch associated with each of said logic modules for selecting as an output signal either the output of the associated logic module or the signal on one of said second conductors; and second tri-state driver means associated with each of said programmable switches, each of said second tri-state driver means being programmable to selectively apply the output signal of the associated programmable switch to one of said first conductors.
Claim 11
Dependent Claim
201 words
A programmable logic array integrated circuit comprising: a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being disposed on said circuit in a two dimensional array; a plurality of first conductors extending substantially parallel to a first dimension of said array; a plurality of second conductors extending substantially parallel to a second dimension of said array; an input pin associated with each of said first conductors; first tri-state driver means associated with each of said first conductors, each of said first tri-state driver means being programmable to selectively apply to the associated first conductor a signal applied to the input pin associated with that first conductor; a programmable switch associated with each of said logic modules for selecting as an output signal either the output of the associated logic module or the signal on one of said second conductors; and second tri-state driver means associated with each of said programmable switches, each of said second tri-state driver means being programmable to selectively apply the output signal of the associated programmable switch to one of said first conductors.
Claim 12
Dependent Claim
29 words
The circuit defined in claim 8 further comprising: programmable memory means associated with each of said first and second tri-state driver means for controlling the associated tri-state driver means.
Claim 13
Dependent Claim
15 words
The circuit defined in claim 8 wherein each of said programmable switches is a multiplexer.
Claim 14
Dependent Claim
22 words
The circuit defined in claim 10 further comprising: programmable memory means associated with each of said multiplexers for controlling the associated multiplexer.
References Cited (Backward Citations)
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