US6002634A — Sense amplifier latch driver circuit for a 1T/1C …

Claim 1

Independent Claim 68 words

A method of driving a sense amplifier having at least one input/output node and at least one latch node the method comprising: initially setting the latch node to a first logic state such that the sense amplifier is disabled; adjusting the latch node voltage in one or more discrete levels; and finally setting the latch node to a second logic state such that the sense amplifier is enabled.

Claim 2

Independent Claim 68 words

A method of driving a sense amplifier having at least one input/output node and at least one latch node the method comprising: initially setting the latch node to a first logic state such that the sense amplifier is disabled; adjusting the latch node voltage in one or more discrete levels; and finally setting the latch node to a second logic state such that the sense amplifier is enabled.

Claim 3

Dependent Claim 22 words

The method of claim 1 in which adjusting the latch node voltage comprises adjusting the latch node voltage in two discrete levels.

Claim 4

Dependent Claim 64 words

The method of claim 1 in which adjusting the latch node voltage comprises: setting the latch node voltage to about three transistor-threshold voltages from the second logic state; maintaining the latch node voltage for a predetermined delay interval; setting the latch node voltage to about two transistor-threshold voltages from the second logic state; and maintaining the latch node voltage for a predetermined delay interval.

Claim 5

Independent Claim 111 words

A method of driving a sense amplifier having at least two input/output nodes, a first latch node coupled to the gate of a P-channel transistor, and a second latch node coupled to the gate of an N-channel transistor, the method comprising: initially setting the first latch node to a logic one state and setting the second latch node to a logic zero state such that the sense amplifier is disabled; adjusting the first latch node voltage in one or more discrete levels; setting the first latch node to a logic zero state; and subsequently setting the second latch node to a logic one state such that the sense amplifier is enabled.

Claim 6

Independent Claim 111 words

A method of driving a sense amplifier having at least two input/output nodes, a first latch node coupled to the gate of a P-channel transistor, and a second latch node coupled to the gate of an N-channel transistor, the method comprising: initially setting the first latch node to a logic one state and setting the second latch node to a logic zero state such that the sense amplifier is disabled; adjusting the first latch node voltage in one or more discrete levels; setting the first latch node to a logic zero state; and subsequently setting the second latch node to a logic one state such that the sense amplifier is enabled.

Claim 7

Dependent Claim 24 words

The method of claim 4 in which adjusting the first latch node voltage comprises adjusting the first latch node voltage in two discrete levels.

Claim 8

Dependent Claim 61 words

The method of claim 4 in which adjusting the first latch node voltage comprises: setting the first latch node voltage to about three transistor-threshold voltages from ground; maintaining the latch node voltage for a predetermined delay interval; setting the first latch node voltage to about two transistor-threshold voltages from ground; and maintaining the latch node voltage for a predetermined delay interval.

Claim 9

Dependent Claim 26 words

The method of claim 6 in which changes in the transistor-threshold voltages substantially track changes in a threshold-voltage of the P-channel transistor in the sense amplifier.

Claim 10

Dependent Claim 78 words

A circuit for driving a sense amplifier comprising: an input node for receiving an input logic signal; an output node for driving the sense amplifier; a first clamp circuit coupled between the input node and the output node; a first delay circuit coupled between the input node and an intermediate node; a second clamp circuit coupled between the intermediate node and the output node; and a second delay circuit coupled between the intermediate node and the output node.

Claim 11

Dependent Claim 78 words

A circuit for driving a sense amplifier comprising: an input node for receiving an input logic signal; an output node for driving the sense amplifier; a first clamp circuit coupled between the input node and the output node; a first delay circuit coupled between the input node and an intermediate node; a second clamp circuit coupled between the intermediate node and the output node; and a second delay circuit coupled between the intermediate node and the output node.

Claim 12

Dependent Claim 16 words

A circuit as in claim 8 in which the first clamp circuit comprises three serially-coupled diodes.

Claim 13

Dependent Claim 15 words

A circuit as in claim 9 in which each diode comprises a diode-connected N-channel transistor.

Claim 14

Dependent Claim 21 words

A circuit as in claim 8 in which the first delay circuit comprises a NOR gate coupled to three serially-connected inverters.

Claim 15

Dependent Claim 16 words

A circuit as in claim 8 in which the second clamp circuit comprises two serially-coupled diodes.

Claim 16

Dependent Claim 15 words

A circuit as in claim 12 in which each diode comprises a diode-connected N-channel transistor.

Claim 17

Dependent Claim 21 words

A circuit as in claim 8 in which the second delay circuit comprises a NOR gate coupled to an N-channel transistor.

Claim 18

Dependent Claim 59 words

A circuit for driving a sense amplifier having first and second latch nodes, the circuit comprising: a first logic circuit having first and second clamp circuits for generating a staircase waveform for driving the first latch node; and a second logic circuit responsive to the first logic circuit for generating a step waveform for driving the second latch node.

Claim 19

Dependent Claim 59 words

A circuit for driving a sense amplifier having first and second latch nodes, the circuit comprising: a first logic circuit having first and second clamp circuits for generating a staircase waveform for driving the first latch node; and a second logic circuit responsive to the first logic circuit for generating a step waveform for driving the second latch node.

Claim 20

Dependent Claim 21 words

The circuit of claim 15 in which the first clamp circuit generates a clamp voltage of about three threshold voltage drops.

Claim 21

Dependent Claim 21 words

The circuit of claim 15 in which the second clamp circuit generates a clamp voltage of about two threshold voltage drops.

Claim 22

Dependent Claim 30 words

The circuit of claim 15 in which the staircase waveform comprises a waveform having four discrete voltage levels comprising VCC, three transistor threshold voltages, two transistor threshold voltages, and ground.

Claim 23

Dependent Claim 17 words

The circuit of claim 15 in which the step waveform is switched from ground to VCC volts.

Claim 24

Dependent Claim 19 words

The circuit of claim 15 further comprising an input logic circuit for receiving first and second input logic signals.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-12-13	2003-06-14	2003-12-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-12-13	2007-06-14	2007-12-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-12-13	2011-06-14	2011-12-14	$7700.00	Window Closed / Lapsed

Sense amplifier latch driver circuit for a 1T/1C ferroelectric memory

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