US5777939A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit line sense amplifier driving circuit of a semiconductor memory device
Assignee: SK Hynix Inc
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Filing: 1996-12-27
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Granted: 1998-07-07
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Expires: 2016-12-27
Abstract
Abstract A bit line sense amplifier driving circuit of a semiconductor memory device which has first and second refresh cycle functions includes a bit line sense amplifier driver unit for supplying a pull-up bias potential signal and a pull-down bias potential signal to a bit line sense amplifier; a bit line sense amplifier predriver unit for controlling the current flowing to the bit line sense amplifier driver unit; and a bit line sense amplifier predriver control unit for controlling the bit line sense amplifier predriver unit according to the first and second refresh cycle functions.
Inventors
- 👤 Jang Kyu Won
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:22
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/406; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
117 words
A bit line sense amplifier driving circuit of a semiconductor memory device which has first and second refresh cycle functions, comprising: bit line sense amplifier driver means for supplying a pull-up bias potential signal and a pull-down bias potential signal to a bit line sense amplifier; bit line sense amplifier predriver means for controlling the current amount of the pull-up bias potential signal and the pull-down bias potential signal of said bit line sense amplifier driver means according to said first and second refresh cycle functions; and bit line sense amplifier predriver control means for controlling said bit line sense amplifier predriver means and generating different logic states according to said first and second refresh cycle functions.
Claim 2
Dependent Claim
117 words
A bit line sense amplifier driving circuit of a semiconductor memory device which has first and second refresh cycle functions, comprising: bit line sense amplifier driver means for supplying a pull-up bias potential signal and a pull-down bias potential signal to a bit line sense amplifier; bit line sense amplifier predriver means for controlling the current amount of the pull-up bias potential signal and the pull-down bias potential signal of said bit line sense amplifier driver means according to said first and second refresh cycle functions; and bit line sense amplifier predriver control means for controlling said bit line sense amplifier predriver means and generating different logic states according to said first and second refresh cycle functions.
Claim 3
Dependent Claim
83 words
The bit line sense amplifier driving circuit as claimed in claim 1, wherein said bit line sense amplifier predriver control means comprise: an input unit which receives a refresh cycle classifying signal for classifying the first refresh cycle and second refresh cycle; a voltage generator for outputting a predetermined level of voltage in response to said refresh cycle classifying signal; and a differential amplifier for comparing and amplifying said predetermined level of voltage output from said voltage generator with a power supply voltage.
Claim 4
Dependent Claim
59 words
The bit line sense amplifier driving circuit as claimed in claim 2, wherein said input unit is means for inverting said refresh cycle classifying signal, and the output signal of said bit line sense amplifier predriver control means is obtained by NORing an inverted signal of the output of said differential amplifier and the output of said input unit.
Claim 5
Dependent Claim
44 words
The bit line sense amplifier driving circuit as claimed in claim 3, wherein said bit line sense amplifier predriver control means output a first logic level under said first refresh cycle function, and output a second logic level under said second refresh cycle function.
Claim 6
Dependent Claim
50 words
The bit line sense amplifier driving circuit as claimed in claim 4, wherein said first refresh cycle is a 1K refresh cycle, said second refresh cycle is a 4k refresh cycle, said first logic level is a logic "low" level and said second logic level is a logic "high" level.
Claim 7
Dependent Claim
101 words
The bit line sense amplifier driving circuit as claimed in claim 1, wherein said bit line sense amplifier predriver means comprise first inverter means, first resistor means connected in series to said first inverter means, second inverter means and second resistor means connected in series to said second inverter means, both ends of said first resistor means being connected in parallel to a first transistor, both ends of said second resistor means being connected in parallel to a second transistor, whereby said first and second transistors are controlled by the output signal of said bit line sense amplifier predriver control means.
Claim 8
Dependent Claim
40 words
The bit line sense amplifier driving circuit as claimed in claim 6, wherein the input signals of said first and second inverter means are predetermined signals corresponding to the output signal of said bit line sense amplifier predriver control means.
Claim 9
Dependent Claim
74 words
The bit line sense amplifier driving circuit as claimed in claim 7, wherein said first inverter means is connected between the power supply voltage and one end of said first resistor means the other end of which is connected to the ground voltage, and said second inverter means is connected between said ground voltage and one end of said second resistor means the other end of which is connected to said power supply voltage.
Claim 10
Dependent Claim
37 words
The bit line sense amplifier driving circuit as claimed in claim 8, wherein said first and second inverter means are CMOS inverters, said first transistor is an NMOS transistor and said second transistor is a PMOS transistor.
Claim 11
Dependent Claim
101 words
The bit line sense amplifier driving circuit as claimed in claim 5, wherein said bit line sense amplifier predriver means comprise first inverter means, first resistor means connected in series to said first inverter means, second inverter means and second resistor means connected in series to said second inverter means, both ends of said first resistor means being connected in parallel to a first transistor, both ends of said second resistor means being connected in parallel to a second transistor, whereby said first and second transistors are controlled by the output signal of said bit line sense amplifier predriver control means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |