US5455786A
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Ferroelectric memory
Assignee: Hitachi Ltd
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Filing: 1994-06-09
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Granted: 1995-10-03
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Expires: 2014-06-09
Abstract
Abstract A highly reliable and high speed ferroelectric memory having high degree of integration is provided. In a ferroelectric memory having a plurality of memory cells M1 each constituted by one transistor and one ferroelectric capacitor. In the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage of a storage node ST1 is utilized as the stored information. Both an electric potential at a plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are made Vcc/2.
Inventors
- 👤 Kan Takeuchi
- 👤 Katsumi Matsuno
- 👤 Yoshinobu Nakagome
- 👤 Masakazu Aoki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C11/221; G11C11/225; G11C11/2273; G11C11/2277; G11C11/2297
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
267 words
A ferroelectric memory comprising: a plurality of memory cells each of which has a capacitor using a ferroelectric material as the dielectric between the electrodes and a field effect transistor; a plurality of data lines each of which is coupled to a source or a drain of the corresponding field effect transistor of each memory cell of said plurality of memory cells; a plurality of word lines each of which is coupled to a gate of the corresponding field effect transistor of each memory cell of said plurality of memory cells; means for supplying stored voltages each showing information which operates to apply a first operating voltage or a second operating voltage to a storage electrode of the capacitor of each memory cell of said plurality of memory cells through a source-drain path of the corresponding field effect transistor; means for supplying an intermediate voltage which operates to apply a third operating voltage, which level is between said first and second operating voltages, to a plate electrode of the capacitor of each memory cell of said plurality of memory cells; a first precharge circuit for precharging, in response to a signal for specifying the read operation of a first mode, the desired data line of said plurality of data lines to a fourth operating voltage, which level is between said first and second operating voltages; and a second precharge circuit for precharging, in response to a signal for specifying the read operation of a second mode, the desired data line of said plurality of data lines to a fifth operating voltage different from said fourth operating voltage.
Claim 2
Dependent Claim
267 words
A ferroelectric memory comprising: a plurality of memory cells each of which has a capacitor using a ferroelectric material as the dielectric between the electrodes and a field effect transistor; a plurality of data lines each of which is coupled to a source or a drain of the corresponding field effect transistor of each memory cell of said plurality of memory cells; a plurality of word lines each of which is coupled to a gate of the corresponding field effect transistor of each memory cell of said plurality of memory cells; means for supplying stored voltages each showing information which operates to apply a first operating voltage or a second operating voltage to a storage electrode of the capacitor of each memory cell of said plurality of memory cells through a source-drain path of the corresponding field effect transistor; means for supplying an intermediate voltage which operates to apply a third operating voltage, which level is between said first and second operating voltages, to a plate electrode of the capacitor of each memory cell of said plurality of memory cells; a first precharge circuit for precharging, in response to a signal for specifying the read operation of a first mode, the desired data line of said plurality of data lines to a fourth operating voltage, which level is between said first and second operating voltages; and a second precharge circuit for precharging, in response to a signal for specifying the read operation of a second mode, the desired data line of said plurality of data lines to a fifth operating voltage different from said fourth operating voltage.
Claim 3
Dependent Claim
28 words
A ferroelectric memory according to claim 1, further comprising means for setting said third and fourth operating voltages of said ferroelectric memory to about the same electric potential.
Claim 4
Dependent Claim
98 words
A ferroelectric memory according to claim 1, further comprising: first detection means for detecting that the second operating voltage supplied to said ferroelectric memory is dropped down to a level equal to or lower than a fixed value; and control means for performing the control in such a way that when an output of said first detection means shows a first state, said first operating voltage is applied to said plurality of word lines and then said first operating voltage is applied to the plate of the capacitor of each memory cell of said plurality of memory cells.
Claim 5
Dependent Claim
115 words
A ferroelectric memory according to claim 1, further comprising: first detection means for detecting that the second operating voltage supplied to said ferroelectric memory reaches a level equal to or higher than a fixed value; and control means for performing the control in such a way that when an output of said first detection means shows a first state, said third operating voltage is applied to the plate electrode of the capacitor of each memory cell of said plurality of memory cells by said intermediate voltage applying means, and said first operating voltage is continued to be applied to said plurality of word lines until said third operating voltage is applied to the plate electrode.
Claim 6
Dependent Claim
107 words
A ferroelectric memory according to claim 1, further comprising: first detection means for detecting that the second operating voltage supplied to said ferroelectric memory reaches a level equal to or higher than a fixed value; and precharge means for precharging, when the stored information in the desired memory cell of said plurality of memory cells is read out, in the case where the operation of reading out the stored information in said desired memory cell is a first read operation after an output of said first detection means shows a first state, the desired data line connected to said desired memory cell to said fifth operating potential.
Claim 7
Dependent Claim
193 words
A ferroelectric memory according to claim 1, further comprising: first detection means for detecting that the second operating voltage supplied to said ferroelectric memory is dropped down to a level equal to or lower than a fixed value; second detection means for detecting that the second operating voltage supplied to said ferroelectric memory reaches a level equal to or higher than a fixed value; and control means for performing the control in such a way that when an output of said first detection means shows a first state, said first operating voltage is applied to said plurality of word lines and then said first operating voltage is applied to the plate of the capacitor of each memory cell of said plurality of memory cells, and when an output of said second detection means shows a second state, said third operating voltage is applied to the plate electrode of the capacitor of each memory cell of said plurality of memory cells by said intermediate voltage applying means, and said first operating voltage is continued to be applied to said plurality of word lines until said third operating voltage is applied to the plate electrode.
Claim 8
Dependent Claim
50 words
A ferroelectric memory according to claim 1, further comprising: a plurality of plate lines each of which is coupled to the corresponding group of memory cells of said plurality of memory cells, wherein said group of memory cells couple to the corresponding word line of said plurality of word lines.
Claim 9
Dependent Claim
42 words
A ferroelectric memory according to claim 1, wherein said first mode is the mode that the ferroelectric memory is treated as a non-volatile memory, and wherein said second mode is the mode that the ferroelectric memory is treated as a volatile memory.
Claim 10
Dependent Claim
171 words
A ferroelectric memory comprising: a plurality of memory cells each of which has a flip-flop circuit including two capacitors each of which uses a ferroelectric material as the dielectric between the electrodes and each of whose storage electrode is coupled to the corresponding storage node of the flip-flop circuit; a plurality of data lines each of which is coupled to the corresponding memory cell of said plurality of memory cells; a plurality of word lines each of which is coupled to the corresponding memory cell of said plurality of memory cells; means for supplying stored voltages each showing information which operates to apply a first operating voltage or a second operating voltage to the storage electrode of the capacitance of each memory cell of said plurality of memory cells; and means for supplying an intermediate voltage which operates to apply a third operating voltage, which level is between said first and second operating voltages, to the plate electrode of the capacitor of each memory cell of said plurality of memory cells.
Claim 11
Dependent Claim
171 words
A ferroelectric memory comprising: a plurality of memory cells each of which has a flip-flop circuit including two capacitors each of which uses a ferroelectric material as the dielectric between the electrodes and each of whose storage electrode is coupled to the corresponding storage node of the flip-flop circuit; a plurality of data lines each of which is coupled to the corresponding memory cell of said plurality of memory cells; a plurality of word lines each of which is coupled to the corresponding memory cell of said plurality of memory cells; means for supplying stored voltages each showing information which operates to apply a first operating voltage or a second operating voltage to the storage electrode of the capacitance of each memory cell of said plurality of memory cells; and means for supplying an intermediate voltage which operates to apply a third operating voltage, which level is between said first and second operating voltages, to the plate electrode of the capacitor of each memory cell of said plurality of memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |