EP0278167A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Self restoring ferroelectric memory
Assignee: Ramtron International Corp
•
Filing: 1987-12-11
•
Granted: —
•
Expires: 2007-12-11
Abstract
Abstract A semiconductor memory uses cells with a ferroelectric capacitor having one plate coupled to a bit line by a FET and another plate coupled to a plate line. A pulse on the plate line causes the bit line to change voltage based on the state of the cell. A dummy cell arrangement is disclosed using one capacitor per cell, and another embodiment uses two capacitors per cell with no dummy. The cells cooperate with a sense amplifier and timing signals so that they are self restoring.
Inventors
- 👤 S. Sheffield Eaton, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 02:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
76 words
A ferroelectric memory comprising: a bit line (26; 60; 86) a sense amplifier (30; 64; 90) coupled to said bit line; a ferroelectric capacitor (22; 52; 83a ); a transistor (24; 56; 81a) coupling one electrode of said ferroelectric capacitor to said bit line; a first line (32; 66; 82 ) coupled to control the operation of said transistor; and a second line (34; 68; 98 ) coupled to the other electrode of said ferroelectric capacitor.
Claim 2
Dependent Claim
76 words
A ferroelectric memory comprising: a bit line (26; 60; 86) a sense amplifier (30; 64; 90) coupled to said bit line; a ferroelectric capacitor (22; 52; 83a ); a transistor (24; 56; 81a) coupling one electrode of said ferroelectric capacitor to said bit line; a first line (32; 66; 82 ) coupled to control the operation of said transistor; and a second line (34; 68; 98 ) coupled to the other electrode of said ferroelectric capacitor.
Claim 3
Dependent Claim
16 words
The memory of claim 1 further comprising a dummy cell (36) coupled to said sense amplifier.
Claim 4
Dependent Claim
18 words
The memory of claim 1 further comprising a second ferroelectric capacitor (58; 83a) coupled to said sense amplifier.
Claim 5
Dependent Claim
58 words
The memory of claim 1 comprising a plurality of memory cells (20a, b, c, d, e; 50a, b, c, . . .; 80a, b, c, d), each having a respective ferroelectric capacitor (22; 52), wherein a pulse (49a, 70) on said second line causes said bit line to change voltage in accordance with the state of said cell.
Claim 6
Dependent Claim
111 words
A ferroelectric memory comprising a plurality of ferroelectric memory cells (50, 50a, b, c . . .; 80a, b, c, d) arranged in rows and columns, each column comprising a pair of bit lines (60, 62; 86, 88, 92, 94) coupled to a respective sense amplifier (64, 64a, b, c, d; 90, 96), each memory cell comprising a pair of ferroelectric capacitors (52, 54; 83a, b, c, d), one coupled selectively to one line of said bit line pair and the other capacitor coupled selectively to the other of said bit line pair; said sense amplifier being responsive to a difference in voltage between the lines of said bit line pair.
Claim 7
Dependent Claim
111 words
A ferroelectric memory comprising a plurality of ferroelectric memory cells (50, 50a, b, c . . .; 80a, b, c, d) arranged in rows and columns, each column comprising a pair of bit lines (60, 62; 86, 88, 92, 94) coupled to a respective sense amplifier (64, 64a, b, c, d; 90, 96), each memory cell comprising a pair of ferroelectric capacitors (52, 54; 83a, b, c, d), one coupled selectively to one line of said bit line pair and the other capacitor coupled selectively to the other of said bit line pair; said sense amplifier being responsive to a difference in voltage between the lines of said bit line pair.
Claim 8
Dependent Claim
90 words
The memory of claim 5 wherein each said sense amplifier (64; 64a, b, c, d; 90, 96) is responsive to a difference in voltages between said bit line pair to drive one of said bit lines (60; 62; 86, 88, 92, 94) to a first voltage and to maintain the other bit line at a reference voltage; and wherein said ferroelectric capacitors in a memory cell have a pair of plates both coupled via a plate line (68; 68a, b, c, d; 98, 100) to a selectively actuable voltage source.
Claim 9
Dependent Claim
59 words
The memory according to claim 6 further comprising, for each said memory cell, a pair of access transistors (56, 58; 81a, b, c, d) each corresponding to a respective ferroelectric capacitor within said memory cell, said transistors being selectively actuable to couple said capacitors to respective bit lines (60, 62; 86, 88, 92, 94) associated with said memory cell.
Claim 10
Dependent Claim
32 words
The memory according to claim 7 including means (138, 140) for applying a voltage (70; 72) to said capacitors of a memory cell and coupling said capacitors to their respective bit lines.
Claim 11
Dependent Claim
31 words
The memory according to claim 8 wherein said means includes a plate line (68; 68a, b, c, d; 98, 100) coupled to the plates of both capacitors in a memory cell.
Claim 12
Dependent Claim
39 words
The memory according to claim 9 wherein said means further includes a word line (66; 66a, b, c, d; 82, 84) coupled to the gate electrodes of the transistors (56, 58; 81a, b, c, d) in a memory cell.
Claim 13
Dependent Claim
26 words
The memory according to claim 10 wherein said word line (66; 66a, b, c, d) is parallel to said plate line (68; 68a, b, c, d).
Claim 14
Dependent Claim
20 words
The memory according to claim 10 wherein said word line (82; 84) is perpendicular to said plate line (100, 102).
Claim 15
Independent Claim
123 words
A method of operating a semiconductor memory comprising the steps of: storing complementary data in a memory cell (50; 50a, b . . .; 80a, b, c, d) having a pair of ferroelectric capacitors; coupling said memory cell to a pair of conductors (60, 62; 60a, b, c, d; 62a, b, c, d; 86, 88, 92, 94); applying a first signal (70) to said capacitors until one said capacitor changes polarization; sensing said change of polarization, driving said pair of conductors in accordance with the data in said cell, and indicating the memory content of said cell; applying a second signal to said memory cell via said conductors after said one capacitor changes polarization to restore said memory cell to its original condition.
Claim 16
Independent Claim
123 words
A method of operating a semiconductor memory comprising the steps of: storing complementary data in a memory cell (50; 50a, b . . .; 80a, b, c, d) having a pair of ferroelectric capacitors; coupling said memory cell to a pair of conductors (60, 62; 60a, b, c, d; 62a, b, c, d; 86, 88, 92, 94); applying a first signal (70) to said capacitors until one said capacitor changes polarization; sensing said change of polarization, driving said pair of conductors in accordance with the data in said cell, and indicating the memory content of said cell; applying a second signal to said memory cell via said conductors after said one capacitor changes polarization to restore said memory cell to its original condition.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.