US5615145A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory with ferroelectric capacitors
Assignee: Rambus Inc
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Filing: 1995-12-20
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Granted: 1997-03-25
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Expires: 2015-12-20
Abstract
Abstract A semiconductor memory which includes a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between the first and second capacitors. The memory cells are arranged at intersections of bit lines and word lines thereby forming a matrix. The first capacitor of each memory cell is a ferroelectric capacitor using a ferroelectric material as an insulating film. A plate electrode of the first capacitor of each memory cell is held at a first potential when the memory is operated in a first mode and the plate electrode of the first capacitor is held at a second potential when the memory is operated in a second mode. The first potential is different from the second potential.
Inventors
- 👤 Kan Takeuchi
- 👤 Katsumi Matsuno
- 👤 Kazuhiko Kajiyama
- 👤 Osamu Nagashima
- 👤 Masatoshi Hasegawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:23
CPC Classifications
G; G11; G11C; G11C16/00; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
145 words
A semiconductor memory comprising: a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between said first and second capacitors, said memory cells being arranged at intersections of bit lines and word lines thereby forming a matrix; wherein said first capacitor is a ferroelectric capacitor using a ferroelectric material as an insulating film; wherein a plate electrode of said first capacitor is held at a power supply potential when said memory is operated in a first mode and said plate electrode of said first capacitor is held at a ground potential when said memory is operated in a second mode; and wherein a plate electrode of said second capacitor is held at a ground potential during a mode changing operation between said first mode and said second mode.
Claim 2
Dependent Claim
145 words
A semiconductor memory comprising: a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between said first and second capacitors, said memory cells being arranged at intersections of bit lines and word lines thereby forming a matrix; wherein said first capacitor is a ferroelectric capacitor using a ferroelectric material as an insulating film; wherein a plate electrode of said first capacitor is held at a power supply potential when said memory is operated in a first mode and said plate electrode of said first capacitor is held at a ground potential when said memory is operated in a second mode; and wherein a plate electrode of said second capacitor is held at a ground potential during a mode changing operation between said first mode and said second mode.
Claim 3
Dependent Claim
41 words
A semiconductor memory according to claim 1, further comprising: a circuit which changes the potential of said plate electrode of said power supply capacitor from said first potential to said ground potential by applying a termination signal to said semiconductor memory.
Claim 4
Dependent Claim
37 words
A semiconductor memory according to claim 2, wherein said termination signal is generated within said semiconductor memory when said power supply potential is detected as having been lowered to a level not higher than a predetermined value.
Claim 5
Dependent Claim
33 words
A semiconductor memory according to claim 2, wherein said termination signal is provided by a same external signal as a self-refresh signal when said semiconductor memory is a Dynamic Random Access Memory (DRAM).
Claim 6
Dependent Claim
67 words
A semiconductor memory according to claim 2, wherein a common plate is provided for said plate electrodes of said first capacitors of said memory cells and said common plate is divided for each memory cell and a potential of said common plate is changed from said power supply potential to said ground potential in such a manner that potentials of divided plates are changed at different timings.
Claim 7
Dependent Claim
35 words
A semiconductor memory according to claim 1, wherein said plate electrode of said first capacitor is changed from said ground potential to said power supply potential by applying a start signal to said semiconductor memory.
Claim 8
Dependent Claim
34 words
A semiconductor memory according to claim 6, wherein said start signal is generated within said semiconductor memory when supply voltage applied to the memory is detected as having reached or exceeded a predetermined value.
Claim 9
Dependent Claim
39 words
A semiconductor memory according to claim 2, further comprising: a register for ordering supply or suspension of said power supply potential to said plate electrode of said power supply capacitor being held at said first potential during normal operation.
Claim 10
Dependent Claim
39 words
A semiconductor memory according to claim 3, further comprising: a register for ordering supply or suspension of said power supply potential to said plate electrode of said power supply capacitor being held at said first potential during normal operation.
Claim 11
Dependent Claim
39 words
A semiconductor memory according to claim 4, further comprising: a register for ordering supply or suspension of said power supply potential to said plate electrode of said power supply capacitor being held at said first potential during normal operation.
Claim 12
Dependent Claim
39 words
A semiconductor memory according to claim 5, further comprising: a register for ordering supply or suspension of said power supply potential to said plate electrode of said power supply capacitor being held at said first potential during normal operation.
Claim 13
Dependent Claim
39 words
A semiconductor memory according to claim 6, further comprising: a register for ordering supply or suspension of said power supply potential to said plate electrode of said power supply capacitor being held at said first potential during normal operation.
Claim 14
Dependent Claim
39 words
A semiconductor memory according to claim 7, further comprising: a register for ordering supply or suspension of said power supply potential to said plate electrode of said power supply capacitor being held at said first potential during normal operation.
Claim 15
Dependent Claim
39 words
A semiconductor memory according to claim 8, further comprising: a register for ordering supply or suspension of said power supply potential to said plate electrode of said power supply capacitor being held at said first potential during normal operation.
Claim 16
Dependent Claim
31 words
A semiconductor memory according to claim 1 wherein data to be stored at said node between said first and second capacitors has a potential between said power supply and ground potentials.
Claim 17
Dependent Claim
27 words
A semiconductor memory according to claim 1 wherein said word lines are held at said ground potential during a transition mode not including reading and writing operations.
Claim 18
Dependent Claim
39 words
A semiconductor memory according to claim 6 wherein said start signal is provided by an external signal when a potential of said plate electrode of said first capacitor is said ground potential, as a RAS signal in a DRAM.
Claim 19
Dependent Claim
69 words
A semiconductor memory according to claim 2 further comprising: means for performing the change of the potential of said plate electrode of said first capacitor after a series of normal operations from activation of one of said word lines to deactivation of said word line when said termination signal is applied to said semiconductor memory after a signal for ordering the activation of said word line has been generated.
References Cited (Backward Citations)
US5383150A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |