Semiconductor memory device having an arrangement to reduce stresses on non-selected ferroelectric capacitors while achieving high integration

Claim 2

A semiconductor memory device having a plurality of subblock memory circuits wherein one electrodes are respectively electrically common-connected to one ends of first switching elements whose control terminals are electrically connected to respective first address selection lines, the other electrodes arranged on a semiconductor substrate side by side in flat form so as to meet at right angles to the one electrodes are set as second address selection lines and ferroelectric capacitors are formed at points where the one electrodes and the other electrodes respectively intersect, said semiconductor memory device being characterized in that different addresses are assigned to the first address selection lines of said plurality of subblock memory circuits, common addresses are respectively assigned to the second address selection lines of said plurality of subblock memory circuits, thereby forming a address selection circuit being in common to the second address selection lines to which the corresponding addresses are assigned, when one of the first address selection lines is in a selected state and the first switching elements are brought into an ON state, one of the plurality of second address selection lines is brought into a selected state and is supplied with a voltage that develops polarization in each of the ferroelectric capacitors and the remaining second address selection lines are brought into such a non-selected potential that a voltage applied to each of the ferroelectric capacitors reaches substantially half the voltage applied to the selected ferroelectric capacitor, and when the first address selection line is brought into a non-selected state and the first switching elements are brought into an OFF state, such a non-selected potential that the voltage applied to each of the ferroelectric capacitors reaches substantially zero is supplied to each of the plurality of second address selection lines.

Claim 3

The semiconductor memory device according to claim 1, wherein the second switching elements are provided on the shared one electrodes side of the ferroelectric capacitors and when the first switching elements of the subblock memory circuit corresponding to the second switching elements are in an ON state, the second switching elements are turned OFF, whereas when the first switching elements of the subblock memory circuit are in an OFF state, the second switching elements are turned ON, thereby supplying a potential identical to that applied to the non-selected second address selection lines to the second switching elements.

Claim 4

The semiconductor memory device according to claim 1, wherein non-selected subblock memory circuits of said plurality of subblock memory circuits are supplied with a precharge voltage substantially equal to half the voltage that develops polarization in the ferroelectric capacitors through the first switching elements, the first switching elements of the subblock memory circuits selected after such a precharge operation has been completed, are turned ON, one of the plurality of second address selection lines is brought into a selected state and is supplied with a voltage that develops polarization in the selected ferroelectric capacitor, and the remaining second address selection lines are set to a non-selected voltage substantially equal to half the voltage applied to the selected ferroelectric capacitor.

Claim 5

The semiconductor memory device according to claim 3, wherein said plurality of subblock memory circuits are arranged in matrix form and X-system addresses are assigned to the first and second address selection lines, and said first switching elements connect the corresponding subblock memory circuit to one of a plurality of signal lines to which Y-system addresses are assigned.

Claim 6

The semiconductor memory device according to claim 4, wherein pairs of switching elements are respectively provided with respect to the plurality of signal lines, the selected one signal line is electrically connected to a common signal line through one switching element and is supplied with a selected voltage, and the remaining non-selected signal lines are supplied with a voltage substantially equal to half the selected voltage through the other switching element.

Claim 7

The semiconductor memory device according to claim 5, wherein control terminals of the pairs of switching elements are respectively complimentarily supplied with signals produced by a Y-system decoder circuit.

Claim 8

The semiconductor memory device according to claim 6, wherein said plurality of subblock memory circuits which respectively share the first and second address selection lines, form one memory block so that a memory access is performed in a memory block unit.

Claim 9

The semiconductor memory device according to claim 7, wherein said memory block is initialized so as to produce polarization on the one side of the ferroelectric capacitors provided in said memory block and only data that reverses the polarization is actually written with the initialization as reference.

Claim 10

The semiconductor memory device according to claim 1, wherein memory cell arrays each having memory cells each comprised of a single switching element and a single ferroelectric capacitor are provided side by side.

Claim 11

The semiconductor memory device according to claim 9, wherein said one electrodes are omitted from the memory cells each comprising the single switching element and the single ferroelectric capacitor and said memory cells are respectively provided with the other electrodes of dummies corresponding to the second selection lines so that layout patterns of the second selection lines are identical in structure to those of said subblock memory circuits.

Claim 12

A semiconductor memory device including a memory block having first and second subblock memory circuits, said first and second subblock memory circuits respectively including: a first address selection line; a data line; a switching element having a first terminal and a second terminal connected to said data line and a control terminal connected to said first address selection line; a first storage element having a first electrode and a second electrode connected to said data line; and a second storage element having a third electrode and a fourth electrode connected to said data line, said first terminal of said switching element in said first subblock memory circuit and said first terminal of said switching element in said second subblock memory circuit being connected to a main data line, said first electrode of said first storage element in said first subblock memory circuit and said first electrode of said first storage element in said second subblock memory circuit being connected to a second address selection line, said third electrode of said second storage element in said first subblock memory circuit and said third electrode of said second storage element in said second subblock memory circuit being connected to a third address selection line, said semiconductor memory device further including a means for controlling the application of a first voltage enabling said first storage element in said first subblock memory circuit to be polarized, between the first and second electrodes of said first storage element in said first subblock memory circuit when said first storage element in said first subblock memory circuit is selected, and controlling the application of a second voltage making unable to polarize said second storage element in said first subblock memory circuit and said first and second storage elements in said second subblock memory circuit, between the third and fourth electrodes of said second storage element in said first subblock memory circuit, between the first and second electrodes of said first storage element in said second subblock memory circuit and between the third and fourth electrodes of said second storage element in said second subblock memory circuit when said first storage element in said first subblock memory circuit is selected.

Claim 13

A semiconductor memory device including a memory block having first and second subblock memory circuits, said first and second subblock memory circuits respectively including: a first address selection line; a data line; a switching element having a first terminal and a second terminal connected to said data line and a control terminal connected to said first address selection line; a first storage element having a first electrode and a second electrode connected to said data line; and a second storage element having a third electrode and a fourth electrode connected to said data line, said first terminal of said switching element in said first subblock memory circuit and said first terminal of said switching element in said second subblock memory circuit being connected to a main data line, said first electrode of said first storage element in said first subblock memory circuit and said first electrode of said first storage element in said second subblock memory circuit being connected to a second address selection line, said third electrode of said second storage element in said first subblock memory circuit and said third electrode of said second storage element in said second subblock memory circuit being connected to a third address selection line, said semiconductor memory device further including a means for controlling the application of a first voltage enabling said first storage element in said first subblock memory circuit to be polarized, between the first and second electrodes of said first storage element in said first subblock memory circuit when said first storage element in said first subblock memory circuit is selected, and controlling the application of a second voltage making unable to polarize said second storage element in said first subblock memory circuit and said first and second storage elements in said second subblock memory circuit, between the third and fourth electrodes of said second storage element in said first subblock memory circuit, between the first and second electrodes of said first storage element in said second subblock memory circuit and between the third and fourth electrodes of said second storage element in said second subblock memory circuit when said first storage element in said first subblock memory circuit is selected.