US5892728A
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US
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Column decoder configuration for a 1T/1C ferroelectric memory
Assignee: Monterey Research LLC
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Filing: 1997-11-14
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Granted: 1999-04-06
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Expires: 2017-11-14
Abstract
Abstract A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
Inventors
- 👤 Judith E. Allen
- 👤 Dennis R. Wilson
- 👤 Joseph J. Perkalis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:44
CPC Classifications
H; H10; H10B; H10B53/00; G; G11; G11C; G11C11/00; G11C11/21; G11C11/22; G11C7/00; G11C7/06; G11C7/065; G11C8/00; G11C8/10; H10B12/00; H10B12/50
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
140 words
A column decoder cell for use in a 1T/1C ferroelectric memory array comprising: a first column decoder section having two input/output nodes for receiving a first input/output signal and a first inverted input/output signal, two bit line nodes for receiving a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal; and a second column decoder section having two input/output nodes for receiving a second input/output signal and a second inverted input/output signal, two bit line nodes for receiving a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
Claim 2
Dependent Claim
140 words
A column decoder cell for use in a 1T/1C ferroelectric memory array comprising: a first column decoder section having two input/output nodes for receiving a first input/output signal and a first inverted input/output signal, two bit line nodes for receiving a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal; and a second column decoder section having two input/output nodes for receiving a second input/output signal and a second inverted input/output signal, two bit line nodes for receiving a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
Claim 3
Dependent Claim
27 words
A column decoder cell as in claim 1 in which the first and second column decoder sections are stacked vertically in the column direction of the array.
Claim 4
Dependent Claim
72 words
A column decoder cell as in claim 1 in which the first column decoder comprises: a first N-channel transistor having a current path coupled between an input/output node and a bit line node, and a gate coupled to the column decode node; and a second N-channel transistor having a current path coupled between the other input/output node and the other bit line node, and a gate coupled to the column decode node.
Claim 5
Dependent Claim
29 words
A column decoder as in claim 3 in which the first column decoder further comprises first and second isolation transistors physically located between the first and second N-channel transistors.
Claim 6
Dependent Claim
29 words
A column decoder cell as in claim 1 in which the first column decoder further comprises first and second isolation transistors having current paths coupled between the input/output nodes.
Claim 7
Dependent Claim
23 words
A column decoder cell as in claim 5 in which the first isolation transistor further comprises a gate for receiving an equilibrate signal.
Claim 8
Dependent Claim
23 words
A column decoder cell as in claim 5 in which the second isolation transistor further comprises a gate that is coupled to ground.
Claim 9
Dependent Claim
71 words
A column decoder cell as in claim 1 in which the second column decoder comprises: a first N-channel transistor having a current path coupled between an input/output node and bit line node, and a gate coupled to the column decode node; and a second N-channel transistor having a current path coupled between the other input/output node and the other bit line node, and a gate coupled to the column decode node.
Claim 10
Dependent Claim
29 words
A column decoder as in claim 8 in which the second column decoder further comprises first and second isolation transistors physically located between the first and second N-channel transistors.
Claim 11
Dependent Claim
29 words
A column decoder cell as in claim 1 in which the second column decoder further comprises first and second isolation transistors having current paths coupled between the input/output nodes.
Claim 12
Dependent Claim
23 words
A column decoder cell as in claim 10 in which the first isolation transistor further comprises a gate for receiving an equilibrate signal.
Claim 13
Dependent Claim
23 words
A column decoder cell as in claim 10 in which the second isolation transistor further comprises a gate that is coupled to ground.
Claim 14
Dependent Claim
149 words
A row of column decoder cells for use in a 1T/1C ferroelectric memory array, each column decoder cell comprising: a first column decoder section having two input/output nodes for receiving a first input/output signal and a first inverted input/output signal, two bit line nodes for receiving a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal; and a second column decoder section having two input/output nodes for receiving a second input/output signal and a second inverted input/output signal, two bit line nodes for receiving a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of each column decoder cell in the row is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
Claim 15
Dependent Claim
149 words
A row of column decoder cells for use in a 1T/1C ferroelectric memory array, each column decoder cell comprising: a first column decoder section having two input/output nodes for receiving a first input/output signal and a first inverted input/output signal, two bit line nodes for receiving a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal; and a second column decoder section having two input/output nodes for receiving a second input/output signal and a second inverted input/output signal, two bit line nodes for receiving a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of each column decoder cell in the row is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
Claim 16
Dependent Claim
27 words
A row of column decoder cells as in claim 13 in which the orientation of every other cell is inverted in the row direction of the array.
Claim 17
Dependent Claim
29 words
A row of column decoder cells as in claim 13 in which the first and second column decoder sections are stacked vertically in the column direction of the array.
Claim 18
Dependent Claim
74 words
A row of column decoder cells as in claim 13 in which the first column decoder comprises: a first N-channel transistor having a current path coupled between an input/output node and a bit line node, and a gate coupled to the column decode node; and a second N-channel transistor having a current path coupled between the other input/output node and the other bit line node, and a gate coupled to the column decode node.
Claim 19
Dependent Claim
32 words
A row of column decoder cells as in claim 13 in which the first column decoder further comprises first and second isolation transistors physically located between the first and second N-channel transistors.
Claim 20
Dependent Claim
60 words
A row of column decoder cells as in claim 13 in which the first column decoder further comprises: a first isolation transistor having a current path coupled between the input/output nodes and a gate for receiving an equilibrate signal; and a second isolation transistor having a current path coupled between the bit line nodes and a gate coupled to ground.
Claim 21
Dependent Claim
74 words
A row of column decoder cells as in claim 13 in which the second column decoder comprises: a first N-channel transistor having a current path coupled between an input/output node and a bit line node, and a gate coupled to the column decode node; and a second N-channel transistor having a current path coupled between the other input/output node and the other bit line node, and a gate coupled to the column decode node.
Claim 22
Dependent Claim
32 words
A row of column decoder cells as in claim 13 in which the second column decoder further comprises first and second isolation transistors physically located between the first and second N-channel transistors.
Claim 23
Dependent Claim
61 words
A row of column decoder cells as in claim 13 in which the second column decoder further comprises: a first isolation transistor having a current path coupled between the bit line nodes and a gate for receiving an equilibrate signal; and a second isolation transistor having a current path coupled between the bit line nodes and a gate coupled to ground.
References Cited (Backward Citations)
US5029128A
Cited
US5010518A
Cited
US5517445A
Cited
US5265061A
Cited
US5038323A
Cited
US5297077A
Cited
US5400275A
Cited
US5086412A
Cited
US5262982A
Cited
US5414654A
Cited
US5455786A
Cited
US5539279A
Cited
US5406510A
Cited
US5517446A
Cited
US5515312A
Cited
US5524093A
Cited
US5615145A
Cited
US5671174A
Cited
US5668753A
Cited
US5508954A
Cited
US5608667A
Cited
US5663904A
Cited
US5638318A
Cited
US5677865A
Cited
US5694353A
Cited
US5745403A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-05 | 2002-10-05 | 2003-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-05 | 2006-10-05 | 2007-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-05 | 2010-10-05 | 2011-04-06 | $7700.00 | Window Closed / Lapsed |