Patent EP0357780A1 successfully refreshed from Google Patents.
Patent US5923982A successfully refreshed from Google Patents.
US5923982A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps
Assignee: GlobalFoundries Inc
•
Filing: 1997-04-21
•
Granted: 1999-07-13
•
Expires: 2017-04-21
Abstract
Abstract A method of making the IGFET includes providing a semiconductor substrate, providing a gate over the semiconductor substrate, implanting lightly doped source and drain regions into the substrate, forming a source-side spacer and a drain-side spacer in close proximity to opposing sidewalls of the gate, forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer, removing the source-side spacer, and implanting a heavily doped drain region and an ultra-heavily doped source region into the substrate after removing the source-side spacer while the drain-side spacer is present, wherein the heavily doped drain region is implanted through the masking layer and the ultra-heavily doped source region is implanted through the opening in the masking layer. Accordingly, the ultra-heavily doped source region has a greater doping concentration than that of the heavily doped drain region due to the masking layer, and a portion of the lightly doped drain region is protected from the second source/drain implant step due to the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.
Inventors
- 👤 Daniel Kadosh
- 👤 Mark I. Gardner
- 👤 Robert Dawson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D64/00; H10D64/01; H10D64/015
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
121 words
A method of making an asymmetrical IGFET, comprising the steps of: providing a semiconductor substrate; providing a gate over the semiconductor substrate; implanting lightly doped source and drain regions into the substrate, forming a source-side spacer and a drain-side spacer to opposing sidewalls of the gate; forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer; and implanting a heavily doped drain region and an ultra-heavily doped source region into the substrate after removing the source-side spacer while the drain-side spacer is present, wherein the heavily doped drain region is implanted through the masking layer and the ultra-heavily doped source region is implanted through the opening in the masking layer.
Claim 2
Independent Claim
121 words
A method of making an asymmetrical IGFET, comprising the steps of: providing a semiconductor substrate; providing a gate over the semiconductor substrate; implanting lightly doped source and drain regions into the substrate, forming a source-side spacer and a drain-side spacer to opposing sidewalls of the gate; forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer; and implanting a heavily doped drain region and an ultra-heavily doped source region into the substrate after removing the source-side spacer while the drain-side spacer is present, wherein the heavily doped drain region is implanted through the masking layer and the ultra-heavily doped source region is implanted through the opening in the masking layer.
Claim 3
Dependent Claim
26 words
The method of claim 1, wherein forming the spacers includes depositing a spacer material over the substrate, and applying an anisotropic etch to the spacer material.
Claim 4
Dependent Claim
11 words
The method of claim 1, wherein the masking layer is photoresist.
Claim 5
Dependent Claim
57 words
The method of claim 1, wherein forming the masking layer includes depositing a masking material over the substrate, forming a photoresist layer over the masking material wherein the photoresist layer covers the drain-side spacer and includes an opening over the source-side spacer, and removing a portion of the masking material beneath the opening in the photoresist layer.
Claim 6
Dependent Claim
112 words
The method of claim 1, wherein forming the masking layer includes depositing a first masking material over the substrate, depositing a second masking material over the first masking material, forming a photoresist layer over the second masking material wherein the photoresist layer covers the drain-side spacer and includes an opening over the source-side spacer, removing a portion of the second masking material beneath the opening in the photoresist layer to provide an opening in the second masking material, stripping the photoresist layer, and then removing a portion of the first masking material beneath the opening in the second masking material, such that the masking layer includes the first and second masking materials.
Claim 7
Dependent Claim
35 words
The method of claim 1, wherein forming the masking layer includes forming a masking material over the source-side spacer and the drain-side spacer, and removing a portion of the masking material over the source-side spacer.
Claim 8
Dependent Claim
21 words
The method of claim 6, including removing the portion of the masking material and the source-side spacer using a single etchant.
Claim 9
Dependent Claim
16 words
The method of claim 7, wherein the masking layer and the source-side spacer are identical materials.
Claim 10
Dependent Claim
20 words
The method of claim 6, including removing the portion of the masking material and the source-side spacer using separate etchants.
Claim 11
Dependent Claim
16 words
The method of claim 9, wherein the masking layer and the source-side spacer include different materials.
Claim 12
Dependent Claim
52 words
The method of claim 1, wherein while implanting the heavily doped drain region, a horizontal portion of the masking layer through which the heavily doped drain region is implanted allows a majority of ions impinging thereon to pass therethrough and blocks a remaining portion of the ions impinging thereon from passing therethrough.
Claim 13
Dependent Claim
41 words
The method of claim 1, wherein a dopant concentration of the ultra-heavily doped source region exceeds that of the heavily doped drain region, and a dopant concentration of the heavily doped drain region exceeds that of the lightly doped drain region.
Claim 14
Dependent Claim
40 words
The method of claim 1, including applying a first ion implantation to form the lightly doped source and drain regions, and then applying a second ion implantation to form the heavily doped drain region and the ultra-heavily doped source region.
Claim 15
Dependent Claim
40 words
The method of claim 1, including applying a first ion implantation to form the heavily doped drain region and the ultra-heavily doped source region, and then applying a second ion implantation to form the lightly doped source and drain regions.
Claim 16
Dependent Claim
35 words
The method of claim 1, including forming a source that includes the ultra-heavily doped source region, and forming a drain that includes the lightly doped and heavily doped drain regions, using two source/drain implant steps.
Claim 17
Dependent Claim
32 words
The method of claim 1, including forming a source that consists of the ultra-heavily doped source region, and forming a drain that consists of the lightly doped and heavily doped drain regions.
Claim 18
Dependent Claim
133 words
The method of claim 1, wherein the steps of: providing a semiconductor substrate; providing a gate over the semiconductor substrate; implanting lightly doped source and drain region into the substrate; forming an insulating layer over the gate and the substrate; forming a source-side spacer and a drain-side spacer to opposing sidewalls of the gate; forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer; and implanting a heavily doped drain region and an ultra-heavily doped source region into the substrate after removing the source-side spacer while the drain-side spacer is present, wherein the heavily doped drain region is implanted through the masking layer and the ultra-heavily doped source region is implanted through the opening in the masking layer, are performed in sequence.
Claim 19
Independent Claim
251 words
A method of making an asymmetrical IGFET, comprising the steps of: providing a semiconductor substrate; forming a gate insulator on the substrate; forming a gate with opposing sidewalls on the gate insulator; applying a first ion implantation to form lightly doped source and drain regions in the substrate using the gate as an implant mask for an underlying portion of the substrate; forming an insulating layer over the gate and the substrate; forming a source-side spacer and a drain-side spacer on the insulating layer and to the opposing sidewalls of the gate, wherein the source-side spacer is over the lightly doped source region and the drain-side spacer is over the lightly doped drain region; forming a masking material over the source-side spacer and the drain-side spacer; removing a portion of the masking material over the source-side spacer to form a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer without removing the drain-side spacer; and then applying a second ion implantation to form an ultra-heavily doped source region and a heavily doped drain region, wherein the ultra-heavily doped source region is implanted through the opening in the masking layer, the heavily doped drain region is implanted through the masking layer, the drain-side spacer provides an implant mask for an underlying portion of the lightly doped drain region, and the ultra-heavily doped source region has a greater doping concentration than that of the heavily doped drain region due to the masking layer.
Claim 20
Independent Claim
251 words
A method of making an asymmetrical IGFET, comprising the steps of: providing a semiconductor substrate; forming a gate insulator on the substrate; forming a gate with opposing sidewalls on the gate insulator; applying a first ion implantation to form lightly doped source and drain regions in the substrate using the gate as an implant mask for an underlying portion of the substrate; forming an insulating layer over the gate and the substrate; forming a source-side spacer and a drain-side spacer on the insulating layer and to the opposing sidewalls of the gate, wherein the source-side spacer is over the lightly doped source region and the drain-side spacer is over the lightly doped drain region; forming a masking material over the source-side spacer and the drain-side spacer; removing a portion of the masking material over the source-side spacer to form a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer without removing the drain-side spacer; and then applying a second ion implantation to form an ultra-heavily doped source region and a heavily doped drain region, wherein the ultra-heavily doped source region is implanted through the opening in the masking layer, the heavily doped drain region is implanted through the masking layer, the drain-side spacer provides an implant mask for an underlying portion of the lightly doped drain region, and the ultra-heavily doped source region has a greater doping concentration than that of the heavily doped drain region due to the masking layer.
Claim 21
Dependent Claim
28 words
The method of claim 18, wherein a source consists of the ultra-heavily doped source regions, and a drain consists of the lightly doped and heavily doped drain regions.
Claim 22
Dependent Claim
26 words
The method of claim 18, wherein the lightly doped drain region and the ultra-heavily doped source region are aligned with the opposing sidewalls of the gate.
Claim 23
Dependent Claim
49 words
The method of claim 18, wherein a dopant concentration of the heavily doped drain region is at least 10 times that of the lightly doped drain region, and a dopant concentration of the ultra-heavily doped source region is at least 1.5 times that of the heavily doped drain region.
Claim 24
Dependent Claim
15 words
The method of claim 18, wherein the masking material and the spacers are identical materials.
Claim 25
Dependent Claim
30 words
The method of claim 22, including forming an etch mask over the masking material, and removing the portion of the masking material and the source-side spacer using a single etchant.
Claim 26
Dependent Claim
15 words
The method of claim 18, wherein the masking material and the spacers include different materials.
Claim 27
Dependent Claim
79 words
The method of claim 24, including depositing a first masking material over the substrate, depositing a second masking material over a first masking material, forming an etch mask over the second masking material, removing a portion of the second masking material using a first wet etch, removing the etch mask, and then removing a portion of the first masking material using a second wet etch, wherein unetched portions of the first and second masking materials form the masking layer.
Claim 28
Dependent Claim
28 words
The method of claim 25, wherein the first masking material and the spacers are identical materials, and the second masking material and the insulating layer are identical materials.
Claim 29
Dependent Claim
35 words
The method of claim 18, wherein the gate is polysilicon, the gate insulator and insulating layer are silicon dioxide, and the spacers are selected from the group consisting of polysilicon, silicon nitride, oxynitride, and aluminum.
Claim 30
Independent Claim
272 words
A method of making an asymmetrical IGFET, comprising the following steps: providing a semiconductor substrate; forming a gate oxide on the substrate; forming a polysilicon gate on the gate oxide; applying a first ion implantation to form lightly doped source and drain regions in the substrate that are aligned with opposing sidewalls of the gate; forming a pad oxide over the substrate, wherein the pad oxide covers a top surface and the opposing sidewalls of the gate; depositing a spacer material on the pad oxide, wherein the spacer material is selected from the group consisting of polysilicon, silicon nitride, silicon oxynitride and aluminum; applying an anisotropic etch to the spacer material to form a source-side spacer and a drain-side spacer on the pad oxide layer and to the opposing sidewalls of the gate, wherein the source-side spacer is over the lightly doped source region and the drain-side spacer is over the lightly doped drain region; forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer without removing the drain-side spacer; and then applying a second ion implantation to form an ultra-heavily doped source region and a heavily doped drain region, wherein the ultra-heavily doped source region is implanted through the opening in the masking layer, the heavily doped region drain region is implanted through the masking layer, the ultra-heavily doped source region has a greater doping concentration than that of the heavily doped drain region due to the masking layer, and a portion of the lightly doped drain region is protected from the second ion implantation due to the drain-side spacer.
Claim 31
Independent Claim
272 words
A method of making an asymmetrical IGFET, comprising the following steps: providing a semiconductor substrate; forming a gate oxide on the substrate; forming a polysilicon gate on the gate oxide; applying a first ion implantation to form lightly doped source and drain regions in the substrate that are aligned with opposing sidewalls of the gate; forming a pad oxide over the substrate, wherein the pad oxide covers a top surface and the opposing sidewalls of the gate; depositing a spacer material on the pad oxide, wherein the spacer material is selected from the group consisting of polysilicon, silicon nitride, silicon oxynitride and aluminum; applying an anisotropic etch to the spacer material to form a source-side spacer and a drain-side spacer on the pad oxide layer and to the opposing sidewalls of the gate, wherein the source-side spacer is over the lightly doped source region and the drain-side spacer is over the lightly doped drain region; forming a masking layer that covers the drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer without removing the drain-side spacer; and then applying a second ion implantation to form an ultra-heavily doped source region and a heavily doped drain region, wherein the ultra-heavily doped source region is implanted through the opening in the masking layer, the heavily doped region drain region is implanted through the masking layer, the ultra-heavily doped source region has a greater doping concentration than that of the heavily doped drain region due to the masking layer, and a portion of the lightly doped drain region is protected from the second ion implantation due to the drain-side spacer.
Claim 32
Dependent Claim
27 words
The method of claim 28, wherein the ultra-heavily doped source region provides a first channel junction, and the lightly doped drain region provides a second channel junction.
Claim 33
Dependent Claim
21 words
The method of claim 29, wherein the first and second channel junctions are aligned with the opposing sidewalls of the gate.
Claim 34
Dependent Claim
56 words
The method of claim 28, wherein during the second ion implantation, a portion of the masking layer, outside the gate and the drain-side spacer, through which the heavily doped drain region is implanted, allows a majority of ions impinging thereon to pass therethrough and blocks a remaining portion of the ions impinging thereon from passing therethrough.
Claim 35
Dependent Claim
11 words
The method of claim 28, wherein the masking layer is photoresist.
Claim 36
Dependent Claim
80 words
The method of claim 28, wherein forming the masking layer includes: depositing a masking layer over the substrate; forming a photoresist over the masking material, wherein the photoresist layer covers the drain-side spacer and includes an opening over the source-side spacer; and applying an etch using the photoresist layer as an etch mask to remove a portion of the masking material beneath the opening in the photoresist layer, wherein an unetched portion of the masking material forms the masking layer.
Claim 37
Dependent Claim
16 words
The method of claim 33, wherein the masking material and the spacer material are silicon nitride.
Claim 38
Dependent Claim
153 words
The method of claim 28, wherein forming the masking layer includes: depositing a first masking material over the substrate; depositing a second masking material over the first masking material; forming a photoresist layer over the second masking material, wherein the photoresist layer covers the drain-side spacer and includes an opening over the source-side spacer; applying a first wet etch using the photoresist layer as an etch mask to remove a portion of the second masking material beneath the opening in the photoresist layer and leave intact an unetched portion of the second masking material; stripping the photoresist layer; and then applying a second wet etch using the unetched portion of the second masking material as an etch mask to remove a portion of the first masking material and leave intact an unetched portion of the first masking material, wherein the unetched portions of the first and second masking materials form the masking layer.
Claim 39
Dependent Claim
273 words
The method of claim 28, wherein the steps of: providing a semiconductor substrate: forming a gate oxide on the substrate; forming a polysilicon gate on the gate oxide; applying a first ion implantation to form lightly doped source and drain regions in the substrate that are aligned with opposing sidewalls of the gate; forming a pad oxide over the substrate, wherein the pad oxide covers a top surface and the opposing sidewalls of the gate; depositing a spacer material on the pad oxide, wherein the spacer material is selected from the group consisting of polysilicon, silicon nitride, silicon oxynitride and aluminum; applying an anisotropic etch to the spacer material to form a source-side spacer and a drain-side spacer on the pad oxide layer and to the opposing sidewalls of the gate, wherein the source-side spacer is over the lightly doped source region and the drain-side spacer is over the lightly doped drain region; forming a masking layer that covers drain-side spacer and includes an opening over the source-side spacer; removing the source-side spacer without removing the drain-side spacer; and then applying a second ion implantation to form an ultra-heavily doped source region and a heavily doped drain region, wherein the ultra-heavily doped source region is implanted through the opening in the masking layer, the heavily doped region drain region is implanted through the masking layer, the ultra-heavily doped source region has a greater doping concentration than that of the heavily doped drain region due to the masking layer, and a portion of the lightly doped drain region is protected from the second ion implantation due to the drain-side spacer; are performed in sequence.
References Cited (Backward Citations)
US4225875A
Cited
US4272881A
Cited
EP0160255A2
Cited
EP0186058A1
Cited
EP0187016A2
Cited
JPS61194777A
Cited
US4927777A
Cited
US5521417A
Cited
US5585658A
Cited
US5073514A
Cited
US5132753A
Cited
US5436482A
Cited
US5547885A
Cited
US5296398A
Cited
JPH0418762A
Cited
US5171700A
Cited
US5424234A
Cited
US5424229A
Cited
US5286664A
Cited
US5200358A
Cited
EP0575099A1
Cited
US5366915A
Cited
US5349225A
Cited
US5451807A
Cited
US5578509A
Cited
US5364807A
Cited
US5397715A
Cited
US5547888A
Cited
US5607869A
Cited
US5518940A
Cited
US5585293A
Cited
JPH0878672A
Cited
US5512503A
Cited
US5510279A
Cited
US5512506A
Cited
US5525552A
Cited
US5672531A
Cited
US5648286A
Cited
US5677224A
Cited
US5759897A
Cited
US5654215A
Cited
US5656518A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |