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US5436482A Expired / Lapsed US ⏱️ 0.0 years remaining

MOSFET with assymetric lightly doped source-drain regions

Assignee: Mitsubishi Electric Corp
•
Filing: 1993-03-31
•
Granted: 1995-07-25
•
Expires: 2013-03-31
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Abstract

Abstract A lightly doped drain MOSFET has lightly doped portions on both the source and drain sides, with the drain side lightly doped portion being wider. The assymetrical structure may be provided by using different width sidewall spacers.

Inventors

  • 👤 Ikuo Ogoh

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 18:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0221; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8316; H10D84/85; H10D84/856; H10D84/8311; H10D84/8312; H10D84/83138; Y; Y10; Y10S; Y10S257/00; Y10S257/90

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 173 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; a first side wall spacer having at least one discrete layer of an insulating film and a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a greater number of discrete layers of an insulating film than said first side wall spacer and a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; and highly doped regions of a second conductivity type extending outwardly from the lightly doped regions.
Claim 2
Dependent Claim 173 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; a first side wall spacer having at least one discrete layer of an insulating film and a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a greater number of discrete layers of an insulating film than said first side wall spacer and a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; and highly doped regions of a second conductivity type extending outwardly from the lightly doped regions.
Claim 3
Dependent Claim 26 words
The semiconductor device in accordance with claim 1, wherein each said layer of the insulating film is formed at slightly different depth in said semiconductor substrate.
Claim 4
Dependent Claim 17 words
A semiconductor device according to claim 1, comprising: an oxide insulating film formed on the gate electrode.
Claim 5
Dependent Claim 26 words
The semiconductor device in accordance with claim 3, wherein each said layer of the insulating film is formed at slightly different depth in said semiconductor substrate.
Claim 6
Dependent Claim 146 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; a first side wall spacer having a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; and highly doped regions of a second conductivity type extending outwardly from the light doped regions.
Claim 7
Dependent Claim 146 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; a first side wall spacer having a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; and highly doped regions of a second conductivity type extending outwardly from the light doped regions.
Claim 8
Dependent Claim 155 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; an oxide insulating film formed on the gate electrode; a first side wall spacer having a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; and highly doped regions of a second conductivity type extending outwardly from the light doped regions.
Claim 9
Dependent Claim 155 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; an oxide insulating film formed on the gate electrode; a first side wall spacer having a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; and highly doped regions of a second conductivity type extending outwardly from the light doped regions.
Claim 10
Dependent Claim 167 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; a first side wall spacer having a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; highly doped regions of a second conductivity type extending outwardly from the light doped regions; and a conductive layer in contact with the heavily doped region adjacent the lightly doped region under the second side wall spacer.
Claim 11
Dependent Claim 167 words
A semiconductor device including a field effect transistor comprising: a semiconductor substrate having a first conductivity type region at least in the vicinity of its surface; a gate electrode formed on said semiconductor substrate with a gate insulating film interposed therebetween; a first side wall spacer having a first predetermined width formed on one side wall surface of said gate electrode; a second side wall spacer having a second predetermined width greater than said first predetermined width formed on the opposite side wall surface of said gate electrode; a lightly doped region of a second conductivity type under each side wall spacer, the lightly doped region under said second side wall spacer having a width greater than the width of the lightly doped region under said first side wall spacer; highly doped regions of a second conductivity type extending outwardly from the light doped regions; and a conductive layer in contact with the heavily doped region adjacent the lightly doped region under the second side wall spacer.
Claim 12
Dependent Claim 17 words
A semiconductor device according to claim 7, comprising an oxide insulating film formed on the gate electrode.
Claim 13
Dependent Claim 20 words
A semiconductor device according to claim 8, wherein said oxide insulating film separates the gate electrode from the conductive layer.

References Cited (Backward Citations)

JPS615571A Cited
US4935379A Cited
EP0244607A1 Cited
US4760033A Cited
JPS63226055A Cited
US4937645A Cited
JPS63246865A Cited
US5061975A Cited
EP0396357A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-07-24 1999-01-23 1999-07-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-07-24 2003-01-23 2003-07-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-07-24 2007-01-23 2007-07-25 $7700.00 Window Closed / Lapsed

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