EP0160255A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Field effect transistor device and method of making same
Assignee: General Electric Co
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Filing: 1985-04-20
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Granted: —
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Expires: 2005-04-20
Abstract
Abstract A field effect transistor with a lightly doped drain and a heavily doped source is formed utilizing a single reactive ion etched silicon dioxide spacer. A gate electrode of polycrystalline silicon on a thin layer of silicon dioxide grown on a silicon substrate of one conductivity type is utilized in the formation of a pair of shallow, lightly doped regions of opposite conductivity type in the substrate on each side of the gate electrode. A pair of silicon dioxide spacers is provided, each on a respective side of the gate electrode and overlying a respective shallow, lightly doped region, by anisotropically etching a layer of silicon dioxide deposited over the structure. One of the spacers is masked and the other spacer is removed by reactive ion etching. Thereafter, a pair of deep, heavily doped regions of opposite conductivity type are formed in the substrate not masked by the gating electrode and the insulating space to complete the formation of the drain and source regions of the device.
Inventors
- 👤 Kirby Gannett Vosburgh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 08:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D64/00; H10D64/01; H10D64/015; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
256 words
A field effect transistor comprising: a substrate of silicon semiconductor material of one conductivity type having a planar surface, a thin layer of insulating material lying on said planar surface, a gate electrode lying on said thin layer of insulating material and having a pair of opposed sides, an insulating spacer including first and second opposed sides and a base, the first side of said spacer being contiguous to one side of said gate electrode and contiguous therewith, the base of said spacer abutting the exposed surface of said thin layer of insulating material, a first shallow region of opposite conductivity type having a first concentration of activators, located adjacent said planar surface and underlying said base of said spacer, said first shallow region forming a first PN junction with said subtrate, a first deep region of opposite conductivity type adjacent said planar surface, said first deep region forming a second PN junction with said said substrate, said second PN junction having an edge in said planar surface and adjacent said second side of said insulating spacer, said first deep region having a second concentration of activators, said second concentration of activators being substantially greater than said first concentration of activators, a second deep region of opposite conductivity type adjacent said planar surface, said second deep region forming a third PN junction having an edge in said planar surface and adjacent said other side of said gate electrode, said second deep region having a third concentration of activators substantially equal to said second concentration of activators.
Claim 2
Dependent Claim
256 words
A field effect transistor comprising: a substrate of silicon semiconductor material of one conductivity type having a planar surface, a thin layer of insulating material lying on said planar surface, a gate electrode lying on said thin layer of insulating material and having a pair of opposed sides, an insulating spacer including first and second opposed sides and a base, the first side of said spacer being contiguous to one side of said gate electrode and contiguous therewith, the base of said spacer abutting the exposed surface of said thin layer of insulating material, a first shallow region of opposite conductivity type having a first concentration of activators, located adjacent said planar surface and underlying said base of said spacer, said first shallow region forming a first PN junction with said subtrate, a first deep region of opposite conductivity type adjacent said planar surface, said first deep region forming a second PN junction with said said substrate, said second PN junction having an edge in said planar surface and adjacent said second side of said insulating spacer, said first deep region having a second concentration of activators, said second concentration of activators being substantially greater than said first concentration of activators, a second deep region of opposite conductivity type adjacent said planar surface, said second deep region forming a third PN junction having an edge in said planar surface and adjacent said other side of said gate electrode, said second deep region having a third concentration of activators substantially equal to said second concentration of activators.
Claim 3
Dependent Claim
24 words
The field effect transistor of claim 1 in which said thin layer of insulating material and said insulating spacer are constituted of silicon dioxide.
Claim 4
Dependent Claim
19 words
The field effect transistor of claim 2 in which said gate electrode is constituted of heavily doped polycrystalline silicon.
Claim 5
Independent Claim
406 words
A method of making a field effect transistor comprising: providing a substrate of silicon semiconductor material of one conductivity type having a planar surface, forming a thin layer of insulating material on said planar surface, forming a gate electrode having a pair of opposite sides on said thin layer of insulating material, forming a first lightly doped shallow region of opposite conductivity type and a second lightly doped shallow region of opposite conductivity type in said substrate adjacent said planar surface, said first shallow region forming a first PN junction with said substrate, said first PN junction having an edge in said planar surface and adjacent one of said sides of said gating electrode, said first shallow region having a first concentration of activators, said second shallow region forming a second PN junction with said substrate, said second PN junction having an edge in said planar surface and adjacent the other of said sides of said gating electrodes, said second shallow region having a second concentration of activators equal to said first concentration of activators, forming a first insulating spacer and a second insulating spacer, each including first and second opposed sides and a base, the first side of said first spacer contiguous to one side of said gate electrode, the bottom base of said first spacer abutting the exposed surface of said thin layer of insulating material, the first side of said second spacer contiguous to the other side of said gate electrode, the bottom base of said second spacer abutting the exposed surface of said thin layer of insulating material, removing said second spacer, forming a first deep region of opposite conductivity type in said electrode adjacent said planar surface, said first deep region forming a third PN junction with said substrate, said third PN junction having an edge in said planar surface and adjacent said second side of said first insulating spacer, said first deep region having a third concentration of activators, said third concentration of activators being substantially greater than said first concentration of activators, forming a second deep region of opposite conductivity type in said substrate adjacent said planar surface, said second deep region forming a fourth PN junction having an edge in said planar surface underlying said other side of said gate electrode, said second deep region having a fourth concentration of activators substantially equal to said third concentration of activators, said fourth deep region containing said second shallow region.
Claim 6
Independent Claim
406 words
A method of making a field effect transistor comprising: providing a substrate of silicon semiconductor material of one conductivity type having a planar surface, forming a thin layer of insulating material on said planar surface, forming a gate electrode having a pair of opposite sides on said thin layer of insulating material, forming a first lightly doped shallow region of opposite conductivity type and a second lightly doped shallow region of opposite conductivity type in said substrate adjacent said planar surface, said first shallow region forming a first PN junction with said substrate, said first PN junction having an edge in said planar surface and adjacent one of said sides of said gating electrode, said first shallow region having a first concentration of activators, said second shallow region forming a second PN junction with said substrate, said second PN junction having an edge in said planar surface and adjacent the other of said sides of said gating electrodes, said second shallow region having a second concentration of activators equal to said first concentration of activators, forming a first insulating spacer and a second insulating spacer, each including first and second opposed sides and a base, the first side of said first spacer contiguous to one side of said gate electrode, the bottom base of said first spacer abutting the exposed surface of said thin layer of insulating material, the first side of said second spacer contiguous to the other side of said gate electrode, the bottom base of said second spacer abutting the exposed surface of said thin layer of insulating material, removing said second spacer, forming a first deep region of opposite conductivity type in said electrode adjacent said planar surface, said first deep region forming a third PN junction with said substrate, said third PN junction having an edge in said planar surface and adjacent said second side of said first insulating spacer, said first deep region having a third concentration of activators, said third concentration of activators being substantially greater than said first concentration of activators, forming a second deep region of opposite conductivity type in said substrate adjacent said planar surface, said second deep region forming a fourth PN junction having an edge in said planar surface underlying said other side of said gate electrode, said second deep region having a fourth concentration of activators substantially equal to said third concentration of activators, said fourth deep region containing said second shallow region.
Claim 7
Dependent Claim
63 words
The method of claim 4 in which said first insulating spacer and said second insulating spacer are formed by depositing a layer of silicon dioxide of a predetermined thickness over said substate and thereafter etching said layer of silicon dioxide anisotropically to the point of exposing the major surface of said substrate thereby forming said first insulating spacer and said second insulating spacer.
Claim 8
Dependent Claim
74 words
The method of claim 5 in which a reactive ion etching mask is provided over a portion of said gate electrode including said one side thereof and over said first insulating spacer, and in which the exposed surface of said substrate is reactive ion etched usinq a gas which reactive ion etches silicon dioxide and which does not reactive ion etch the material of said gate electrode thereby selectively removing said second insulating spacer.
Claim 9
Dependent Claim
17 words
The method of claim 6 in which said gate electrode is constituted of heavily doped polycrystalline silicon.
Claim 10
Dependent Claim
12 words
The method of claim 7 in which said gas is trifluoro- methane.
References Cited (Backward Citations)
No citation records indexed.
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