Method for fabrication of a non-symmetrical transistor

Claim 1

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming a first sidewall oxide region and a second sidewall oxide region adjacent the first and second sidewalls, respectively; increasing the size of the second sidewall oxide region while the size of the first sidewall oxide region remains substantially constant; and then implanting a second dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 2

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming a first sidewall oxide region and a second sidewall oxide region adjacent the first and second sidewalls, respectively; increasing the size of the second sidewall oxide region while the size of the first sidewall oxide region remains substantially constant; and then implanting a second dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 24

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: (1) forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; (2) implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; (3) forming an oxide layer over the semiconductor substrate outside of the gate electrode, the top surface of the gate electrode and the first and second sidewalls of the gate electrode wherein the oxide layer adjacent the first and second sidewalls, respectively, provides first and second sidewall oxide regions, respectively; (4) isolating the first sidewall oxide region; (5) thermally growing the oxide of the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant; (6) exposing the first sidewall oxide region; and (7) implanting a second dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 25

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: (1) forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; (2) implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; (3) forming an oxide layer over the semiconductor substrate outside of the gate electrode, the top surface of the gate electrode and the first and second sidewalls of the gate electrode wherein the oxide layer adjacent the first and second sidewalls, respectively, provides first and second sidewall oxide regions, respectively; (4) isolating the first sidewall oxide region; (5) thermally growing the oxide of the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant; (6) exposing the first sidewall oxide region; and (7) implanting a second dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 30

A method for fabrication of a non-symmetrical IGFET comprising the of steps of: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall and a lightly doped source region substantially aligned with the first sidewall; forming an oxide layer over the semiconductor substrate outside of the polysilicon electrode, the top surface of the polysilicon electrode and the first and second sidewalls wherein the oxide layer adjacent the first and second sidewalls provides first and second sidewall oxide regions, respectively; forming a nitride layer over the oxide layer; forming a photoresist film that covers the nitride layer above the first sidewall oxide region and exposes the nitride layer above the second sidewall oxide region; etching the portion of the nitride layer exposed through the opening in the photoresist film to provide an opening in the nitride layer wherein the second sidewall oxide region is exposed through the opening in the nitride layer and the first sidewall oxide region is isolated by the nitride layer; removing the photoresist film; thermally growing the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant; removing the nitride layer; and then implanting a second dopant into the semiconductor substrate to provide a heavily doped drain region substantially aligned with the outside edge of the second sidewall oxide region and a heavily doped source region.

Claim 31

A method for fabrication of a non-symmetrical IGFET comprising the of steps of: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall and a lightly doped source region substantially aligned with the first sidewall; forming an oxide layer over the semiconductor substrate outside of the polysilicon electrode, the top surface of the polysilicon electrode and the first and second sidewalls wherein the oxide layer adjacent the first and second sidewalls provides first and second sidewall oxide regions, respectively; forming a nitride layer over the oxide layer; forming a photoresist film that covers the nitride layer above the first sidewall oxide region and exposes the nitride layer above the second sidewall oxide region; etching the portion of the nitride layer exposed through the opening in the photoresist film to provide an opening in the nitride layer wherein the second sidewall oxide region is exposed through the opening in the nitride layer and the first sidewall oxide region is isolated by the nitride layer; removing the photoresist film; thermally growing the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant; removing the nitride layer; and then implanting a second dopant into the semiconductor substrate to provide a heavily doped drain region substantially aligned with the outside edge of the second sidewall oxide region and a heavily doped source region.