US5585658A
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Semiconductor device having diffusion regions formed with an ion beam absorber pattern
Assignee: Mitsubishi Electric Corp
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Filing: 1995-06-07
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Granted: 1996-12-17
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Expires: 2015-06-07
Abstract
Abstract In implantation of ions into a wafer, in the manufacture of a semiconductor device, a desired ion beam absorber pattern having locally different thicknesses is previously formed on a major surface of the wafer. The ion beam absorber pattern absorbs an ion beam to be implanted and is formed of a thin film material with its absorbency varying depending on its thickness. Ions are implanted once on the major surface of the wafer through this ion beam absorber pattern to form desired different impurity profiles in depth of desired regions on the major surface of the wafer.
Inventors
- 👤 Takao Mukai
- 👤 Nobuyuki Yoshioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:39
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/22; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; Y; Y10; Y10S; Y10S148/00; Y10S148/106; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/949; Y10S438/965
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
291 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first source/drain region comprising: a first diffusion layer of a second conductivity type having a first depth and a first impurity concentration formed in the major surface of said semiconductor substrate; a second diffusion layer of said second conductivity type having a second depth and a second impurity concentration formed in the major surface of said semiconductor substrate in direct contact with said first diffusion layer, and extending from said first diffusion layer a first distance parallel to said semiconductor substrate; and a second source/drain region spaced apart from said first source/drain region with a channel region therebetween, said second source/drain region comprising: a third diffusion layer of said second conductivity type having a third depth and a third impurity concentration spaced apart from said second diffusion layer in the major surface of said semiconductor substrate by said channel region; a fourth diffusion layer of said second conductivity type having said first depth and said first impurity concentration formed in the major surface of said semiconductor substrate in direct contact with said third diffusion layer, said third diffusion layer extending from said fourth diffusion layer a second distance, greater than the first distance, parallel to said semiconductor substrate; and a gate electrode formed on the major surface of said semiconductor substrate over said channel region between said second and third diffusion layers and extending over portions of said second and third diffusion layers; said first depth being larger than said second depth, said second depth being larger than said third depth, said first impurity concentration being higher than said second impurity concentration, and said second impurity concentration being higher than said third impurity concentration.
Claim 2
Dependent Claim
291 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first source/drain region comprising: a first diffusion layer of a second conductivity type having a first depth and a first impurity concentration formed in the major surface of said semiconductor substrate; a second diffusion layer of said second conductivity type having a second depth and a second impurity concentration formed in the major surface of said semiconductor substrate in direct contact with said first diffusion layer, and extending from said first diffusion layer a first distance parallel to said semiconductor substrate; and a second source/drain region spaced apart from said first source/drain region with a channel region therebetween, said second source/drain region comprising: a third diffusion layer of said second conductivity type having a third depth and a third impurity concentration spaced apart from said second diffusion layer in the major surface of said semiconductor substrate by said channel region; a fourth diffusion layer of said second conductivity type having said first depth and said first impurity concentration formed in the major surface of said semiconductor substrate in direct contact with said third diffusion layer, said third diffusion layer extending from said fourth diffusion layer a second distance, greater than the first distance, parallel to said semiconductor substrate; and a gate electrode formed on the major surface of said semiconductor substrate over said channel region between said second and third diffusion layers and extending over portions of said second and third diffusion layers; said first depth being larger than said second depth, said second depth being larger than said third depth, said first impurity concentration being higher than said second impurity concentration, and said second impurity concentration being higher than said third impurity concentration.
Claim 3
Dependent Claim
323 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first source/drain region comprising: a first diffusion layer of a second conductivity type having a first depth and a first impurity concentration formed in the major surface of said semiconductor substrate; a second diffusion layer of said second conductivity type having a second depth and a second impurity concentration formed in the major surface of said semiconductor substrate and contacting said first diffusion layer through a first interface region, and extending from said first interface region a first distance parallel to said semiconductor substrate; and a second source/drain region spaced apart from said first source/drain region with a channel region therebetween, said second source/drain region comprising: a third diffusion layer of said second conductivity type having a third depth and a third impurity concentration spaced apart from said second diffusion layer in the major surface of said semiconductor substrate by said channel region; a fourth diffusion layer of said second conductivity type having said first depth and said first impurity concentration formed in the major surface of said semiconductor substrate and contacting said third diffusion layer through a second interface region, said third diffusion layer extending from said second interface region a second distance, greater than the first distance, parallel to said semiconductor substrate; and a gate electrode formed on the major surface of said semiconductor substrate over said channel region between said second and third diffusion layers and extending over portions of said second and third diffusion layers; said first depth being larger than said second depth, said second depth being larger than said third depth, said first impurity concentration being higher than said second impurity concentration, and said second impurity concentration being higher than said third impurity concentration, wherein the impurity profile of the first source/drain region increases in concentration and depth in a stepwise or gradual manner extending away from said gate electrode.
Claim 4
Dependent Claim
323 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first source/drain region comprising: a first diffusion layer of a second conductivity type having a first depth and a first impurity concentration formed in the major surface of said semiconductor substrate; a second diffusion layer of said second conductivity type having a second depth and a second impurity concentration formed in the major surface of said semiconductor substrate and contacting said first diffusion layer through a first interface region, and extending from said first interface region a first distance parallel to said semiconductor substrate; and a second source/drain region spaced apart from said first source/drain region with a channel region therebetween, said second source/drain region comprising: a third diffusion layer of said second conductivity type having a third depth and a third impurity concentration spaced apart from said second diffusion layer in the major surface of said semiconductor substrate by said channel region; a fourth diffusion layer of said second conductivity type having said first depth and said first impurity concentration formed in the major surface of said semiconductor substrate and contacting said third diffusion layer through a second interface region, said third diffusion layer extending from said second interface region a second distance, greater than the first distance, parallel to said semiconductor substrate; and a gate electrode formed on the major surface of said semiconductor substrate over said channel region between said second and third diffusion layers and extending over portions of said second and third diffusion layers; said first depth being larger than said second depth, said second depth being larger than said third depth, said first impurity concentration being higher than said second impurity concentration, and said second impurity concentration being higher than said third impurity concentration, wherein the impurity profile of the first source/drain region increases in concentration and depth in a stepwise or gradual manner extending away from said gate electrode.
Claim 5
Dependent Claim
323 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first source/drain region comprising: a first diffusion layer of a second conductivity type having a first depth and a first impurity concentration formed in the major surface of said semiconductor substrate; a second diffusion layer of said second conductivity type having a second depth and a second impurity concentration formed in the major surface of said semiconductor substrate and contacting said first diffusion layer through a first interface region, and extending from said first interface region a first distance parallel to said semiconductor substrate; and a second source/drain region spaced apart from said first source/drain region with a channel region therebetween, said second source/drain region comprising: a third diffusion layer of said second conductivity type having a third depth and a third impurity concentration spaced apart from said second diffusion layer in the major surface of said semiconductor substrate by said channel region; a fourth diffusion layer of said second conductivity type having said first depth and said first impurity concentration formed in the major surface of said semiconductor and contacting said third diffusion layer substrate through a second interface region, said third diffusion layer extending from said second interface region a second distance, greater than the first distance, parallel to said semiconductor substrate; and a gate electrode formed on the major surface of said semiconductor substrate over said channel region between said second and third diffusion layers and extending over portions of said second and third diffusion layers; said first depth being larger than said second depth, said second depth being larger than said third depth, said first impurity concentration being higher than said second impurity concentration, and said second impurity concentration being higher than said third impurity concentration, wherein the impurity profile of the second source/drain region increases in concentration and depth in a stepwise or gradual manner extending away from said gate electrode.
Claim 6
Dependent Claim
323 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first source/drain region comprising: a first diffusion layer of a second conductivity type having a first depth and a first impurity concentration formed in the major surface of said semiconductor substrate; a second diffusion layer of said second conductivity type having a second depth and a second impurity concentration formed in the major surface of said semiconductor substrate and contacting said first diffusion layer through a first interface region, and extending from said first interface region a first distance parallel to said semiconductor substrate; and a second source/drain region spaced apart from said first source/drain region with a channel region therebetween, said second source/drain region comprising: a third diffusion layer of said second conductivity type having a third depth and a third impurity concentration spaced apart from said second diffusion layer in the major surface of said semiconductor substrate by said channel region; a fourth diffusion layer of said second conductivity type having said first depth and said first impurity concentration formed in the major surface of said semiconductor and contacting said third diffusion layer substrate through a second interface region, said third diffusion layer extending from said second interface region a second distance, greater than the first distance, parallel to said semiconductor substrate; and a gate electrode formed on the major surface of said semiconductor substrate over said channel region between said second and third diffusion layers and extending over portions of said second and third diffusion layers; said first depth being larger than said second depth, said second depth being larger than said third depth, said first impurity concentration being higher than said second impurity concentration, and said second impurity concentration being higher than said third impurity concentration, wherein the impurity profile of the second source/drain region increases in concentration and depth in a stepwise or gradual manner extending away from said gate electrode.
Claim 7
Dependent Claim
33 words
A semiconductor device according to claim 2, wherein the impurity profile of the second source/drain region increases in concentration and depth in a stepwise or gradual manner extending away from said gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |