Insulated gate semiconductor device and manufacture thereof
Abstract
Abstract PURPOSE:To increase the hot carrier withstand quantity and to reduce a para sitic resistance by forming insulating spacers connected with the side planes of a gate unsymmetrically and effecting the ion implantation of low concentra tion impurity by using said spacers as a mask. CONSTITUTION:On the principal surface of a high specific resistance p<-> type Si substrate 1, an isolation oxide film 2, a gate oxide film 3, and a gate 4 consisting of polysilicon are formed. By using the gate 4 and the oxide film 2 as a mask, the ion implantation of phosphorus impurity is done to form a low concentration impurity layer 7 on the surface of the substrate 1. Next, an oxide film 6 is formed for forming spacers. Subsequently, As ions are implanted over the entire surface to form a high concentration impurity layer on the surface of the substrate. A heat treatment is made to diffuse the impurity such as P and As in the substrate 1 and a low concentration n<-> layer 8 on the surface of the substrate right under the spacer 6, and at the same time, a high concentration n<+> layer 7 are formed. After that, an insulating film 9 is produced and a source and drain Al electrode 10 is formed. Thus, the n- channel MOSFET of LDD structure is completed.
Inventors
- 👤 Akira Muramatsu
- 👤 彰 村松
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.