Process for fabricating self-aligned silicide lightly doped drain MOS devices

Claim 1

A method of fabricating an MOS integrated circuit, said method comprising the steps of: providing a silicon substrate; prior to the formation of source and drain regions in the upper surface of said substrate, defining a polysilicon gate on the upper surface of said substrate; depositing a layer of a first material over said polysilicon gate and over at least a part of the exposed upper surface of said substrate, said first material having a different etch characteristic as compared to that of said silicon substrate; depositing and forming by etching a side wall spacer about said polysilicon gate of a second material having a different etching characteristic than said first material, said first layer serving as an etching stop; thereafter removing said first layer in regions of the upper surface of said substrate and said polysilicon gate not covered by said side wall spacer; depositing a metal and thereafter reacting said metal with the exposed surfaces of said substrate and said polysilicon gate, thereby to form a layer of a silicide of said metal thereat of a thickness such that said silicide layer has substantially less ion implant stopping power than said first layer; thereafter removing said side wall spacer; and thereafter performing sequentially a light and a heavy ion implant of the same dopant impurity through said silicide layer and said first layer, thereby to form source and drain regions in the upper surface of said substrate.

Claim 2

A method of fabricating an MOS integrated circuit, said method comprising the steps of: providing a silicon substrate; prior to the formation of source and drain regions in the upper surface of said substrate, defining a polysilicon gate on the upper surface of said substrate; depositing a layer of a first material over said polysilicon gate and over at least a part of the exposed upper surface of said substrate, said first material having a different etch characteristic as compared to that of said silicon substrate; depositing and forming by etching a side wall spacer about said polysilicon gate of a second material having a different etching characteristic than said first material, said first layer serving as an etching stop; thereafter removing said first layer in regions of the upper surface of said substrate and said polysilicon gate not covered by said side wall spacer; depositing a metal and thereafter reacting said metal with the exposed surfaces of said substrate and said polysilicon gate, thereby to form a layer of a silicide of said metal thereat of a thickness such that said silicide layer has substantially less ion implant stopping power than said first layer; thereafter removing said side wall spacer; and thereafter performing sequentially a light and a heavy ion implant of the same dopant impurity through said silicide layer and said first layer, thereby to form source and drain regions in the upper surface of said substrate.