Method for fabrication of a non-symmetrical transistor

Claim 1

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls defining a length of the gate electrode; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming first and second spacers adjacent to the first and second sidewalls, respectively, after implanting the first dopant; removing a portion of the gate electrode adjacent to the first sidewall, after forming the spacers, to form a third sidewall of the gate electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the gate electrode; and implanting a second dopant into the semiconductor substrate after forming the third sidewall to provide a heavily doped source region substantially aligned with the third sidewall.

Claim 2

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls defining a length of the gate electrode; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming first and second spacers adjacent to the first and second sidewalls, respectively, after implanting the first dopant; removing a portion of the gate electrode adjacent to the first sidewall, after forming the spacers, to form a third sidewall of the gate electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the gate electrode; and implanting a second dopant into the semiconductor substrate after forming the third sidewall to provide a heavily doped source region substantially aligned with the third sidewall.

Claim 5

The method of claim I further comprising implanting a third dopant into the semiconductor substrate adjacent to and outside of the gate electrode and the spacers before forming the third sidewall.

Claim 24

A method for fabrication of a non-symmetrical IGFET comprising the sequence of steps of: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls defining a length of the polysilicon electrode; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the second sidewall; depositing an oxide layer to cover the surface of the semiconductor substrate, the first and second sidewalls of the polysilicon electrode and the top surface of the polysilicon electrode; removing the oxide layer from the top surface of the polysilicon electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the first and second sidewalls of the polysilicon electrode to form first and second spacers adjacent to the first and second sidewalls, respectively; forming a photoresist layer over the lightly doped drain region, the second spacer, the second sidewall and a part of the top surface of the polysilicon electrode, the photoresist layer having an opening which exposes a portion of the polysilicon electrode, the first spacer and the first sidewall; etching the portion of the polysilicon electrode exposed through the opening in the photoresist layer to form a third sidewall of the polysilicon electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the polysilicon electrode; etching the first spacer; removing the photoresist layer; and implanting a heavily doped source region into the semiconductor substrate and substantially aligned with the third sidewall and a heavily doped drain region into the semiconductor substrate and adjacent to and outside of the second spacer.

Claim 25

A method for fabrication of a non-symmetrical IGFET comprising the sequence of steps of: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls defining a length of the polysilicon electrode; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the second sidewall; depositing an oxide layer to cover the surface of the semiconductor substrate, the first and second sidewalls of the polysilicon electrode and the top surface of the polysilicon electrode; removing the oxide layer from the top surface of the polysilicon electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the first and second sidewalls of the polysilicon electrode to form first and second spacers adjacent to the first and second sidewalls, respectively; forming a photoresist layer over the lightly doped drain region, the second spacer, the second sidewall and a part of the top surface of the polysilicon electrode, the photoresist layer having an opening which exposes a portion of the polysilicon electrode, the first spacer and the first sidewall; etching the portion of the polysilicon electrode exposed through the opening in the photoresist layer to form a third sidewall of the polysilicon electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the polysilicon electrode; etching the first spacer; removing the photoresist layer; and implanting a heavily doped source region into the semiconductor substrate and substantially aligned with the third sidewall and a heavily doped drain region into the semiconductor substrate and adjacent to and outside of the second spacer.

Claim 26

A method for fabrication of a non-symmetrical IGFET comprising the sequence of steps of: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls defining a length of the polysilicon electrode; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the second sidewall; depositing an oxide layer to cover the surface of the semiconductor substrate, the first and second sidewalls of the polysilicon electrode and the top surface of the polysilicon electrode; removing the oxide layer from the top surface of the polysilicon electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the first and second sidewalls of the polysilicon electrode to form first and second spacers adjacent to the first and second sidewalls, respectively; implanting a heavily doped drain region into the semiconductor substrate adjacent to and outside of the second spacer and a first portion of a heavily doped source region adjacent to and outside the first spacer; forming a photoresist layer over the lightly doped drain region, the heavily doped drain region, the second spacer, the second sidewall and a part of the top surface of the polysilicon electrode, the photoresist layer having an opening which exposes a portion of the polysilicon electrode, the first spacer and the first sidewall; etching the portion oil the polysilicon electrode exposed through the opening in the photoresist layer to form a third sidewall of the polysilicon electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the polysilicon electrode; etching the first spacer; and implanting a second portion of a heavily doped source region into the semiconductor substrate and substantially aligned with the third sidewall.

Claim 27

A method for fabrication of a non-symmetrical IGFET comprising the sequence of steps of: providing a semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls defining a length of the polysilicon electrode; implanting a lightly doped drain region into the semiconductor substrate and substantially aligned with the second sidewall; depositing an oxide layer to cover the surface of the semiconductor substrate, the first and second sidewalls of the polysilicon electrode and the top surface of the polysilicon electrode; removing the oxide layer from the top surface of the polysilicon electrode and from above a portion of the surface of the semiconductor substrate outside and spaced from the first and second sidewalls of the polysilicon electrode to form first and second spacers adjacent to the first and second sidewalls, respectively; implanting a heavily doped drain region into the semiconductor substrate adjacent to and outside of the second spacer and a first portion of a heavily doped source region adjacent to and outside the first spacer; forming a photoresist layer over the lightly doped drain region, the heavily doped drain region, the second spacer, the second sidewall and a part of the top surface of the polysilicon electrode, the photoresist layer having an opening which exposes a portion of the polysilicon electrode, the first spacer and the first sidewall; etching the portion oil the polysilicon electrode exposed through the opening in the photoresist layer to form a third sidewall of the polysilicon electrode opposite the second sidewall, thereby eliminating the first sidewall and reducing the length of the polysilicon electrode; etching the first spacer; and implanting a second portion of a heavily doped source region into the semiconductor substrate and substantially aligned with the third sidewall.