Patent US5898638A successfully refreshed from Google Patents.
US5898638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Latching wordline driver for multi-bank memory
Assignee: Round Rock Research LLC
•
Filing: 1997-03-11
•
Granted: 1999-04-27
•
Expires: 2017-03-11
Abstract
Abstract A memory device is described which includes latching wordline driver circuits. The wordline driver circuits include a latch responsive to phase lines of an address tree decode configuration. The latch has been described as a single latching transistor which allows transitions in shared row address lines while maintaining an active wordline signal. The latching wordline driver is particularly useful in multi-bank memory devices where row address lines are shared between the memory banks.
Inventors
- 👤 Brent Keeth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:29
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/08
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
73 words
A memory device comprising: a multiple bank array of memory cells; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; and a wordline driver circuit for generating the wordline signal in response to address signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals.
Claim 2
Dependent Claim
73 words
A memory device comprising: a multiple bank array of memory cells; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; and a wordline driver circuit for generating the wordline signal in response to address signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals.
Claim 3
Dependent Claim
27 words
The memory device of claim 1 wherein the wordline driver circuit further generates the wordline signal in response to a memory bank dependant signal, and phase signals.
Claim 4
Dependent Claim
93 words
A memory device comprising: a multiple bank array of memory cells; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; and a wordline driver circuit for generating the wordline signal in response to address signals the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals the worldline driver circuit further generates the worldline signal in response to a sense amplifier activation signal, and phase signal.
Claim 5
Dependent Claim
93 words
A memory device comprising: a multiple bank array of memory cells; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; and a wordline driver circuit for generating the wordline signal in response to address signals the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals the worldline driver circuit further generates the worldline signal in response to a sense amplifier activation signal, and phase signal.
Claim 6
Dependent Claim
129 words
A memory device comprising: a multiple bank array of memory cells; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; and a wordline driver circuit for generating the wordline signal in response to address signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals, wherein the wordline driver circuit comprises: a tree decode circuit for decoding address signals and phase signals; a level translator connected to the tree decode circuit for generating a wordline signal in response to the tree decode circuit; and a latch circuit connected to the level translator for latching an active state of the wordline signal.
Claim 7
Dependent Claim
129 words
A memory device comprising: a multiple bank array of memory cells; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; and a wordline driver circuit for generating the wordline signal in response to address signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals, wherein the wordline driver circuit comprises: a tree decode circuit for decoding address signals and phase signals; a level translator connected to the tree decode circuit for generating a wordline signal in response to the tree decode circuit; and a latch circuit connected to the level translator for latching an active state of the wordline signal.
Claim 8
Dependent Claim
13 words
The memory device of claim 4 wherein the latch circuit is a transistor.
Claim 9
Dependent Claim
117 words
A memory device comprising: an array of memory cells, the array arranged in multiple banks of memory cells; address input lines shared between the multiple banks of memory cells for receiving address signals; decode circuitry for decoding the received address signals and generating phase signals; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; a wordline driver circuit for generating the wordline signal in response to the received address signals, a memory bank dependant signal and the phase signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals.
Claim 10
Dependent Claim
117 words
A memory device comprising: an array of memory cells, the array arranged in multiple banks of memory cells; address input lines shared between the multiple banks of memory cells for receiving address signals; decode circuitry for decoding the received address signals and generating phase signals; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; a wordline driver circuit for generating the wordline signal in response to the received address signals, a memory bank dependant signal and the phase signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals.
Claim 11
Dependent Claim
17 words
The memory device of claim 6 wherein the memory device is a synchronous dynamic random access memory.
Claim 12
Dependent Claim
117 words
A memory device comprising: an array of memory cells, the array arranged in multiple banks of memory cells; address input lines shared between the multiple banks of memory cells for receiving address signals; decode circuitry for decoding the received address signals and generating phase signals; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; a wordline driver circuit for generating the wordline signal in response to the received address signals, a sense amplifier activation signal and the phase signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals.
Claim 13
Dependent Claim
117 words
A memory device comprising: an array of memory cells, the array arranged in multiple banks of memory cells; address input lines shared between the multiple banks of memory cells for receiving address signals; decode circuitry for decoding the received address signals and generating phase signals; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; a wordline driver circuit for generating the wordline signal in response to the received address signals, a sense amplifier activation signal and the phase signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals.
Claim 14
Dependent Claim
173 words
A memory device comprising: an array of memory cells the array arranged in multiple banks of memory cells; address input lines shared between the multiple banks of memory cells for receiving address signals; decode circuitry for decoding the received address signals and generating phase signals; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; a wordline driver circuit for generating the wordline signal in response to the received address signals, a memory array bank dependant signal and the phase signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals, the wordline driver circuit comprises: a tree decode circuit for decoding address signals and phase signals; a level translator connected to the tree decode circuit for generating a wordline signal in response to the tree decode circuit; and a latch transistor connected to the level translator for latching an active state of the wordline signal.
Claim 15
Dependent Claim
173 words
A memory device comprising: an array of memory cells the array arranged in multiple banks of memory cells; address input lines shared between the multiple banks of memory cells for receiving address signals; decode circuitry for decoding the received address signals and generating phase signals; access devices coupled to the memory cells for accessing the memory cells in response to a wordline signal; a wordline driver circuit for generating the wordline signal in response to the received address signals, a memory array bank dependant signal and the phase signals, the wordline driver circuit including a latch for latching an active state of the wordline signal so that the wordline signal becomes independent of transitions of the address signals, the wordline driver circuit comprises: a tree decode circuit for decoding address signals and phase signals; a level translator connected to the tree decode circuit for generating a wordline signal in response to the tree decode circuit; and a latch transistor connected to the level translator for latching an active state of the wordline signal.
Claim 16
Dependent Claim
87 words
A latching wordline driver circuit for use in a memory device comprising: a decode tree comprising a series of pass transistors coupled between a local phase line and an input of a level translator, the level translator having an output coupled to a wordline; a pulldown transistor having a drain connected to the wordline and a gate coupled to the local phase line; and a latch circuit coupled between the local phase line and the input of the level translator to latch a signal on the wordline.
Claim 17
Dependent Claim
87 words
A latching wordline driver circuit for use in a memory device comprising: a decode tree comprising a series of pass transistors coupled between a local phase line and an input of a level translator, the level translator having an output coupled to a wordline; a pulldown transistor having a drain connected to the wordline and a gate coupled to the local phase line; and a latch circuit coupled between the local phase line and the input of the level translator to latch a signal on the wordline.
Claim 18
Dependent Claim
26 words
The latching wordline driver circuit of claim 10 wherein the series of pass transistors are activated by row address signals and a memory array bank signal.
Claim 19
Dependent Claim
20 words
The latching wordline driver circuit of claim 11 wherein the memory array bank signal is a sense amplifier activation signal.
Claim 20
Dependent Claim
41 words
The latching wordline driver circuit of claim 10 wherein the latch circuit is a transistor having a drain coupled to the input of the level translator, a source coupled to the local phase line, and a gate coupled to the wordline.
Claim 21
Independent Claim
72 words
A method of accessing a memory device, the method comprising the steps of: providing a first set of address signals to the memory device; decoding the first address signals; generating a first wordline signal based upon the decoded address signals; accessing a first row of memory cells based on the first set of address signals; and latching the first wordline signal in an active state to allow transitions in the address signals.
Claim 22
Independent Claim
72 words
A method of accessing a memory device, the method comprising the steps of: providing a first set of address signals to the memory device; decoding the first address signals; generating a first wordline signal based upon the decoded address signals; accessing a first row of memory cells based on the first set of address signals; and latching the first wordline signal in an active state to allow transitions in the address signals.
Claim 23
Dependent Claim
17 words
The method of claim 14 wherein the step of decoding produces row address signals and phase signals.
Claim 24
Dependent Claim
62 words
The method of claim 14 further comprising the steps in the order of: providing a second set of address signals to the memory device, after the step of latching; decoding the second address signals; generating a second wordline signal based upon the decoded second address signals; and accessing a second row of memory cells based on the second set of address signals.
References Cited (Backward Citations)
US4096402A
Cited
US4404474A
Cited
US4638187A
Cited
US4638187B1
Cited
US4789796A
Cited
US4984204A
Cited
JPH02112317A
Cited
US4958088A
Cited
US5165046A
Cited
EP0450871A2
Cited
US5513327A
Cited
US5473575A
Cited
JPH04135311A
Cited
US5122690A
Cited
US5128563A
Cited
US5150186A
Cited
US5128560A
Cited
JPH05136664A
Cited
JPH05282868A
Cited
US5278460A
Cited
US5361002A
Cited
US5254883A
Cited
US5274276A
Cited
US5311481A
Cited
US5347177A
Cited
US5347179A
Cited
EP0655741A2
Cited
US5400283A
Cited
US5574698A
Cited
US5438545A
Cited
EP0680049A2
Cited
US5694065A
Cited
US5568077A
Cited
US5578941A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |