US5894565A — Field programmable gate array with distributed RA…

Claim 1

Independent Claim 137 words

A logic circuit comprising, non-dedicated logic cells arranged in a plurality of identical blocks, each block having a plurality of said logic cells, the blocks of cells laid out in a grid pattern of multiple rows and columns of blocks, with cells within each block communicating with each other along paths internal to the blocks, the blocks of cells communicating with each other along paths through repeaters which lie between said rows and columns of blocks, leaving spaces at the corners of each of the blocks of cells, and dedicated function elements disposed at said corners of each of the plurality of blocks of cells in said spaces and communicating with the cells of corresponding blocks via said paths internal to the blocks, each dedicated function element constructed to carry out a specific logic or memory function.

Claim 2

Dependent Claim 137 words

A logic circuit comprising, non-dedicated logic cells arranged in a plurality of identical blocks, each block having a plurality of said logic cells, the blocks of cells laid out in a grid pattern of multiple rows and columns of blocks, with cells within each block communicating with each other along paths internal to the blocks, the blocks of cells communicating with each other along paths through repeaters which lie between said rows and columns of blocks, leaving spaces at the corners of each of the blocks of cells, and dedicated function elements disposed at said corners of each of the plurality of blocks of cells in said spaces and communicating with the cells of corresponding blocks via said paths internal to the blocks, each dedicated function element constructed to carry out a specific logic or memory function.

Claim 3

Dependent Claim 40 words

The logic circuit of claim 1 wherein said dedicated function elements comprise user-accessible multibit memory structures for providing a memory function whereby said memory structures may be addressed, and data stored in and retrieved from said structures, via said paths.

Claim 4

Dependent Claim 15 words

The logic circuit of claim 2 wherein said memory structures comprise multibit-addressable nonvolatile memory blocks.

Claim 5

Dependent Claim 21 words

The logic circuit of claim 1 wherein said dedicated function elements comprise specialized logic structures for carrying out specific logic function.

Claim 6

Dependent Claim 115 words

A logic circuit comprising: non-dedicated logic cells arranged in identical blocks, the blocks of cells laid out in a grid pattern of rows and columns, with cells communicating with each other along paths internal to the blocks, the blocks communicating with each other along paths through repeaters which lie between said rows and columns of blocks, leaving spaces at the corners of the blocks; and multipliers disposed at said corners of each of the blocks in said spaces and communicating with the cells of corresponding blocks via said paths internal to the blocks, each multiplier constructed to carry out arithmetic multiplication of a pair of multibit inputs to provide a multibit product of said inputs.

Claim 7

Dependent Claim 115 words

A logic circuit comprising: non-dedicated logic cells arranged in identical blocks, the blocks of cells laid out in a grid pattern of rows and columns, with cells communicating with each other along paths internal to the blocks, the blocks communicating with each other along paths through repeaters which lie between said rows and columns of blocks, leaving spaces at the corners of the blocks; and multipliers disposed at said corners of each of the blocks in said spaces and communicating with the cells of corresponding blocks via said paths internal to the blocks, each multiplier constructed to carry out arithmetic multiplication of a pair of multibit inputs to provide a multibit product of said inputs.

Claim 8

Dependent Claim 216 words

A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells, a bus network including a set of bus lines distributed along the rows and columns of logic cells and a set of repeater switch units spaced along said bus lines and selectively connecting associated bus lines to each other, the set of bus lines including local bus lines connectable to logic cells and express bus lines not directly connectable to logic cells but connectable by means of said repeater switch units to associated local bus lines, wherein said matrix of logic cells is organized as a plurality of blocks of cells, each block having a plurality of said logic cells, with said repeater switch units located between said blocks aligned in rows and columns and arranged around perimeters of said blocks of cells, the repeater switch units thereby allowing express bus lines connected thereto to span more than one block of logic cells, and a plurality of dedicated function elements located at corners of each of said plurality of blocks of logic cells where said rows and columns of repeater switch units intersect, said dedicated function elements coupled to said bus network, wherein each dedicated function element has been constructed to carry out a specific logic or memory function.

Claim 9

Dependent Claim 216 words

A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells, a bus network including a set of bus lines distributed along the rows and columns of logic cells and a set of repeater switch units spaced along said bus lines and selectively connecting associated bus lines to each other, the set of bus lines including local bus lines connectable to logic cells and express bus lines not directly connectable to logic cells but connectable by means of said repeater switch units to associated local bus lines, wherein said matrix of logic cells is organized as a plurality of blocks of cells, each block having a plurality of said logic cells, with said repeater switch units located between said blocks aligned in rows and columns and arranged around perimeters of said blocks of cells, the repeater switch units thereby allowing express bus lines connected thereto to span more than one block of logic cells, and a plurality of dedicated function elements located at corners of each of said plurality of blocks of logic cells where said rows and columns of repeater switch units intersect, said dedicated function elements coupled to said bus network, wherein each dedicated function element has been constructed to carry out a specific logic or memory function.

Claim 10

Dependent Claim 22 words

The FPGA of claim 6 wherein said dedicated function elements are specialized arithmetic structures for carrying out a specific arithmetic-type logic function.

Claim 11

Dependent Claim 40 words

The FPGA of claim 6 wherein said dedicated function elements are user-accessible, multibit-addressable memory structures for providing a memory function whereby said memory structures may be addressed, and data stored in and read from said structures, via said bus network.

Claim 12

Dependent Claim 15 words

The FPGA of claim 8 wherein said memory structures comprise random access memory (RAM) blocks.

Claim 13

Dependent Claim 13 words

The FPGA of claim 8 wherein said memory structures comprise nonvolatile memory blocks.

Claim 14

Dependent Claim 25 words

The FPGA of claim 8 wherein said memory structures comprise dual-port memory with separate address inputs for read and write operations and separate data busses.

Claim 15

Dependent Claim 237 words

A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells; a bus network including a set of bus lines distributed along the rows and columns of logic cells and a set of repeater switch units spaced along said bus lines and selectively connecting associated bus lines to each other, the set of bus lines including local bus lines connectable to logic cells and express bus lines not directly connectable to logic cells but connectable by means of said repeater switch units to associated local bus lines, wherein said matrix of logic cells is organized as blocks of cells with said repeater switch units located between said blocks aligned in rows and columns and arranged around perimeters of said blocks of cells, the repeater switch units thereby allowing express bus lines connected thereto to span more than one block of logic cells; and a plurality of user-accessible, multibit-addressable memory structures located at corners of each of said blocks of logic cells where said rows and columns of repeater switch units intersect, said memory structures coupled to said bus network, each multibit-addressable memory structure constructed to provide a memory function whereby said memory structures may be addressed, and data stored in and read from said structures, via said bus network, wherein adjacent columns of said memory structures are addressable by bus lines associated with the same columns of blocks of logic cells.

Claim 16

Dependent Claim 237 words

A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells; a bus network including a set of bus lines distributed along the rows and columns of logic cells and a set of repeater switch units spaced along said bus lines and selectively connecting associated bus lines to each other, the set of bus lines including local bus lines connectable to logic cells and express bus lines not directly connectable to logic cells but connectable by means of said repeater switch units to associated local bus lines, wherein said matrix of logic cells is organized as blocks of cells with said repeater switch units located between said blocks aligned in rows and columns and arranged around perimeters of said blocks of cells, the repeater switch units thereby allowing express bus lines connected thereto to span more than one block of logic cells; and a plurality of user-accessible, multibit-addressable memory structures located at corners of each of said blocks of logic cells where said rows and columns of repeater switch units intersect, said memory structures coupled to said bus network, each multibit-addressable memory structure constructed to provide a memory function whereby said memory structures may be addressed, and data stored in and read from said structures, via said bus network, wherein adjacent columns of said memory structures are addressable by bus lines associated with the same columns of blocks of logic cells.

Claim 17

Dependent Claim 177 words

A field programmable gate array (FPGA), comprising: a set of input and output terminals, a set of bus lines, at least some of which are coupled to said terminals, said set of bus lines including a set of local bus lines, a set of express bus lines, and a set of repeater switch units connecting local bus lines to said express bus lines, a plurality of programmable logic cells, each cell having connections to said set of local bus lines, said logic cells being organized into a plurality of blocks of cells, each block having a plurality of said logic cells, wherein each block of cells is connectable to an associated set of local bus lines for that block but not to local bus lines associated with other blocks of cells, said express bus lines spanning multiple blocks of cells, and a plurality of user-accessible multibit memory structures, each multibit memory structure associated with a block of cells and having a plurality of address and data ports connectable to bus lines associated with that block of cells.

Claim 18

Dependent Claim 177 words

A field programmable gate array (FPGA), comprising: a set of input and output terminals, a set of bus lines, at least some of which are coupled to said terminals, said set of bus lines including a set of local bus lines, a set of express bus lines, and a set of repeater switch units connecting local bus lines to said express bus lines, a plurality of programmable logic cells, each cell having connections to said set of local bus lines, said logic cells being organized into a plurality of blocks of cells, each block having a plurality of said logic cells, wherein each block of cells is connectable to an associated set of local bus lines for that block but not to local bus lines associated with other blocks of cells, said express bus lines spanning multiple blocks of cells, and a plurality of user-accessible multibit memory structures, each multibit memory structure associated with a block of cells and having a plurality of address and data ports connectable to bus lines associated with that block of cells.

Claim 19

Dependent Claim 77 words

The FPGA of claim 13 wherein said logic cells are arranged in a matrix of rows and columns of cells, said cells arranged as rectilinear blocks separated by rows and columns of repeater switch units with said set of bus lines running horizontally and vertically along said rows and columns of cells, each said memory structure being located at the corners of said blocks of cells at intersections of said rows and columns of repeater switch units.

Claim 20

Dependent Claim 127 words

A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells, and a bus network distributed between the rows and columns of cells, including a set of local bus lines directly connectable to said logic cells and a set of express bus lines that are not directly connectable to said logic cells but connectable to local bus lines by means of repeater switch units spaced along said local and express bus lines, such that said express bus lines can communicate with said logic cells only through said local bus lines, pairs of express bus lines being connected to repeater switch units in a staggered manner such that consecutive repeater switch units alternately connect to different express bus lines of the pair.

Claim 21

Dependent Claim 127 words

A field programmable gate array (FPGA), comprising: a matrix of rows and columns of programmable logic cells, and a bus network distributed between the rows and columns of cells, including a set of local bus lines directly connectable to said logic cells and a set of express bus lines that are not directly connectable to said logic cells but connectable to local bus lines by means of repeater switch units spaced along said local and express bus lines, such that said express bus lines can communicate with said logic cells only through said local bus lines, pairs of express bus lines being connected to repeater switch units in a staggered manner such that consecutive repeater switch units alternately connect to different express bus lines of the pair.

Claim 22

Dependent Claim 95 words

A field programmable gate array (FPGA), comprising: a set of input and output terminals, a set of bus lines, at least some of said bus lines being coupled to said terminals, said set of bus lines including a set of local bus lines, a set of express bus lines, and a set of repeater switch units connecting local bus lines to said express bus lines, and a plurality of programmable logic cells, each cell having connections to said set of local bus lines, wherein each express bus line is connected to non-consecutive repeater switch units.

Claim 23

Dependent Claim 95 words

A field programmable gate array (FPGA), comprising: a set of input and output terminals, a set of bus lines, at least some of said bus lines being coupled to said terminals, said set of bus lines including a set of local bus lines, a set of express bus lines, and a set of repeater switch units connecting local bus lines to said express bus lines, and a plurality of programmable logic cells, each cell having connections to said set of local bus lines, wherein each express bus line is connected to non-consecutive repeater switch units.

Claim 24

Dependent Claim 42 words

The FPGA of claim 16 wherein said logic cells are arranged in a matrix of rows and columns of cells and are organized as an N×N block of cells, where said repeater switch units are regularly spaced after every N logic cells.

Claim 25

Dependent Claim 7 words

The FPGA of claim 17 wherein N=4.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-04-12	2002-10-12	2003-04-13	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-04-12	2006-10-12	2007-04-13	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-04-12	2010-10-12	2011-04-13	$7700.00	Window Closed / Lapsed

Field programmable gate array with distributed RAM and increased cell utilization

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