US5204556A
Expired / Lapsed
US
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Programmable interconnect structure for logic blocks
Assignee: Lattice Semiconductor Corp
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Filing: 1991-05-06
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Granted: 1993-04-20
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Expires: 2011-05-06
Abstract
Abstract A structure for making programmable connections between the input and output terminals of individual logic blocks in a logic device is disclosed. In one embodiment, each output terminal is programmably connected to only one input terminal of each logic block. The same principle is followed in making connections between the input pins of the device and the input terminals of the logic blocks.
Inventors
- 👤 Kapil Shankar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:18
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17704; H03K19/17724; H03K19/17728
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
215 words
A programmable interconnect structure comprising: a plurality of logic blocks, each of said logic blocks having a plurality of input terminals and a plurality of output terminals, the number of output terminals of each logic block being less than the number of input terminals of said logic block; an input channel to each of said one or more logic blocks, each input channel comprising a plurality of input lines connected to predetermined input terminals of a predetermined one of said logic blocks; a plurality of signal routing channels, each of said signal routing channels comprising a plurality of signal routing lines; said logic blocks being grouped into one or more megacells, each of said megacells containing more than one logic block, the output terminals of the logic blocks in each of said megacells being connected to predetermined signal routing lines in a predetermined one of said signal routing channels; and a matrix of programmable connections between each of said input channels and each of said signal routing channels wherein the number of said programmable connections in each said matrix is less than the number of input lines in said matrix multiplied by the number of signal routing lines in said matrix and equal to or greater than the number of input lines in said matrix.
Claim 2
Dependent Claim
215 words
A programmable interconnect structure comprising: a plurality of logic blocks, each of said logic blocks having a plurality of input terminals and a plurality of output terminals, the number of output terminals of each logic block being less than the number of input terminals of said logic block; an input channel to each of said one or more logic blocks, each input channel comprising a plurality of input lines connected to predetermined input terminals of a predetermined one of said logic blocks; a plurality of signal routing channels, each of said signal routing channels comprising a plurality of signal routing lines; said logic blocks being grouped into one or more megacells, each of said megacells containing more than one logic block, the output terminals of the logic blocks in each of said megacells being connected to predetermined signal routing lines in a predetermined one of said signal routing channels; and a matrix of programmable connections between each of said input channels and each of said signal routing channels wherein the number of said programmable connections in each said matrix is less than the number of input lines in said matrix multiplied by the number of signal routing lines in said matrix and equal to or greater than the number of input lines in said matrix.
Claim 3
Dependent Claim
36 words
The programmable interconnect structure of claim 1 wherein the number of output terminals of the logic blocks in each of said megacells is equal to the number of input terminals of each of said logic blocks.
Claim 4
Dependent Claim
30 words
The programmable interconnect structure of claim 1 wherein each of said signal routing lines is programmably connected to only one of said input lines in each of said input channels.
Claim 5
Dependent Claim
47 words
The programmable interconnect structure of claim 1 comprising a plurality of device terminals, said device terminals being separated into groups, the device terminals in each of said groups being connected through input/output cells to predetermined signal routing lines in a predetermined one of said signal routing channels.
Claim 6
Dependent Claim
56 words
The programmable interconnect structure of claim 1 comprising a plurality of resource routing lines and a plurality of device terminals, predetermined ones of said output terminals being programmably connectable to predetermined ones of said resource routing lines, predetermined ones of said resource routing lines being connected through input/output cells to predetermined ones of said device terminals.
Claim 7
Dependent Claim
90 words
The programmable interconnect structure of claim 1 comprising: a plurality of device terminals, said device terminals being separated into groups, the device terminals in each of said groups being connected through input/output cells to predetermined signal routing lines in a predetermined one of said signal routing channels; and a plurality of resource routing lines, predetermined ones of said output terminals being programmably connectable to predetermined ones of said resource routing lines, predetermined ones of said resource routing lines being connected through input/output cells to predetermined ones of said device terminals.
Claim 8
Dependent Claim
90 words
A programmable logic device comprising a plurality of logic blocks, each of said logic blocks having a plurality of input terminals connected to respective input lines and a plurality of output terminals connected to respective output lines, and a plurality of device terminals, wherein each of said output lines is programmably connectable to at least one but less than all of the input lines for each of said logic blocks, and predetermined ones of said output terminals are programmably connectable through input/output cells to predetermined ones of said device terminals.
Claim 9
Dependent Claim
90 words
A programmable logic device comprising a plurality of logic blocks, each of said logic blocks having a plurality of input terminals connected to respective input lines and a plurality of output terminals connected to respective output lines, and a plurality of device terminals, wherein each of said output lines is programmably connectable to at least one but less than all of the input lines for each of said logic blocks, and predetermined ones of said output terminals are programmably connectable through input/output cells to predetermined ones of said device terminals.
Claim 10
Dependent Claim
90 words
A programmable logic device comprising a plurality of logic blocks, each of said logic blocks having a plurality of input terminals connected to respective input lines and a plurality of output terminals connected to respective output lines, and a plurality of device terminals, wherein each of said device terminals is programmably connectable to at least one but less than all of the input lines for each of said logic blocks, and predetermined ones of said output terminals are programmably connectable through input/output cells to predetermined ones of said device terminals.
Claim 11
Dependent Claim
90 words
A programmable logic device comprising a plurality of logic blocks, each of said logic blocks having a plurality of input terminals connected to respective input lines and a plurality of output terminals connected to respective output lines, and a plurality of device terminals, wherein each of said device terminals is programmably connectable to at least one but less than all of the input lines for each of said logic blocks, and predetermined ones of said output terminals are programmably connectable through input/output cells to predetermined ones of said device terminals.
Claim 12
Dependent Claim
122 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks is in the sum of the products form.
Claim 13
Dependent Claim
122 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks is in the sum of the products form.
Claim 14
Dependent Claim
120 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals though input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable logic device (PLD).
Claim 15
Dependent Claim
120 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals though input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable logic device (PLD).
Claim 16
Dependent Claim
123 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable array logic/generic array logic circuit (PAL/GAL).
Claim 17
Dependent Claim
123 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable array logic/generic array logic circuit (PAL/GAL).
Claim 18
Dependent Claim
120 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable logic array (PLA).
Claim 19
Dependent Claim
120 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable logic array (PLA).
Claim 20
Dependent Claim
120 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said input routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a random access memory (RAM).
Claim 21
Dependent Claim
120 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said input routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a random access memory (RAM).
Claim 22
Dependent Claim
121 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable read only memory (PROM).
Claim 23
Dependent Claim
121 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a programmable read only memory (PROM).
Claim 24
Dependent Claim
122 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said control routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises an erasable programmable read only memory (EPROM).
Claim 25
Dependent Claim
122 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said control routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises an erasable programmable read only memory (EPROM).
Claim 26
Dependent Claim
123 words
A programmable logic device comprising; a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises an electrically erasable programmable read only memory (EEPROM).
Claim 27
Dependent Claim
123 words
A programmable logic device comprising; a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises an electrically erasable programmable read only memory (EEPROM).
Claim 28
Dependent Claim
119 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a combination of multiplexers.
Claim 29
Dependent Claim
119 words
A programmable logic device comprising: a plurality of programmable logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, said programmable connections being located outside of said logic blocks; wherein at least one of said device terminals is programmably connectable via said output routing resource arrangement to output terminals in two or more of said logic blocks; and wherein at least one of said logic blocks comprises a combination of multiplexers.
Claim 30
Dependent Claim
93 words
A programmable logic device comprising: a plurality of logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, wherein one, and only one, of said programmable connections need be programmed in order to connect one of said output terminals to one of said device terminals.
Claim 31
Dependent Claim
93 words
A programmable logic device comprising: a plurality of logic blocks, each of said logic blocks comprising a plurality of input terminals and a plurality of output terminals; a plurality of device terminals; an output routing resource arrangement, said output routing resource arrangement comprising a plurality of programmable connections for connecting individual ones of said output terminals through input/output cells to individual ones of said device terminals, wherein one, and only one, of said programmable connections need be programmed in order to connect one of said output terminals to one of said device terminals.
Claim 32
Dependent Claim
33 words
The programmable logic device of claim 18 wherein at least one of said output terminals is programmably connectable via said output routing resource arrangement to two or more of said device terminals simultaneously.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |