US4965472A
Expired / Lapsed
US
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Programmable high speed state machine with sequencing capabilities
Assignee: Cypress Semiconductor Corp
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Filing: 1988-08-11
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Granted: 1990-10-23
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Expires: 2008-08-11
Abstract
Abstract Programmable high speed state machines with sequencing capabilities based on a dual array structure with state information and fast sequencing logic placed between the two arrays are disclosed. The state section consists of multiple registered macrocells which are connected to function as program counters and decoders to the output array. The input array has feedback from the state registers and input from the dedicated inputs and input/output pins around the device. The inputs of the input array are all individually configurable as registered or nonregistered, with the inputs being divided into three groups, input/output, Mealy and simple inputs, with three enable product terms from the output array controlling the respective groups. Various additional characteristics, features and capabilities of the invention are disclosed.
Inventors
- 👤 Robert E. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:51
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
147 words
A programmable state machine comprising: a plurality of clocked macrocells, each having a state register, said macrocells having a cascade input and a cascade output, said cascade output being responsive to the state of said state register in the respective said macrocell, said macrocells having the cascade output of one macrocell coupled to the cascade input of the next macrocell, each of said macrocells being programmably responsive to a condition input and the cascade input to control the state transitions of the state register therein; a programmable input array coupled to said macrocells for logically combining state machine inputs to provide said condition inputs to said macrocell; and, a programmable output array coupled to said macrocells and responsive to the state of said state register in each said macrocell to provide state machine outputs responsive to the state machine inputs and the programming of said state machine.
Claim 2
Dependent Claim
147 words
A programmable state machine comprising: a plurality of clocked macrocells, each having a state register, said macrocells having a cascade input and a cascade output, said cascade output being responsive to the state of said state register in the respective said macrocell, said macrocells having the cascade output of one macrocell coupled to the cascade input of the next macrocell, each of said macrocells being programmably responsive to a condition input and the cascade input to control the state transitions of the state register therein; a programmable input array coupled to said macrocells for logically combining state machine inputs to provide said condition inputs to said macrocell; and, a programmable output array coupled to said macrocells and responsive to the state of said state register in each said macrocell to provide state machine outputs responsive to the state machine inputs and the programming of said state machine.
Claim 3
Dependent Claim
59 words
The programmable state machine of claim 1 wherein said programmable input array is an AND gate array, and includes inverters so as to be responsive to the state machine inputs and the inverse thereof to provide as the condition inputs to said macrocells, the AND of an AND and an OR of the state machine inputs and current state.
Claim 4
Dependent Claim
71 words
The programmable state machine of claim 2 wherein each macrocell is programmable to execute one of at least three operations, including (i) a start operation responsive to an input to set the respective state register for one clock cycle, (ii) a toggle operation responsive to an input to change the state of the respective state register, and (iii) a terminate operation responsive to an input to reset the respective state register.
Claim 5
Dependent Claim
18 words
The programmable state machine of claim 2 wherein said programmable output array is a programmable OR gate array.
Claim 6
Dependent Claim
67 words
The programmable state machine of claim 1 further including feedback means for feeding the state register outputs from said macrocells back to said input array, whereby said input array may be programmed to provide as condition inputs to any of said macrocells, the state register output of any one or more of said macrocells alone or in combination with the logical combination of the state machine inputs.
Claim 7
Dependent Claim
208 words
A programmable state machine comprising: a plurality of clocked macrocells, each having a state register, said macrocells having a cascade input and a cascade output, said cascade output being responsive to the state of said state register in the respective said macrocell, said macrocells having the cascade output of one macrocell coupled to the cascade input of the next macrocell, each of said macrocells being programmably responsive to a condition input and the cascade input to control the state of the state register therein; a programmable AND gate input array coupled to said macrocells for logically combining state machine inputs to provide said condition inputs to said macrocell; a programmable OR gate output array coupled to said macrocells and responsive to the state of said state register in each said macrocell to provide state machine outputs responsive to the state machine inputs and the programming of said state machine, and, feedback means for feeding the state register outputs from said macrocells back to said input array, whereby said input array may be programmed to provide as condition inputs to any of said macrocells, the state register output of any one or more of said macrocells alone or in combination with the logical combination of the state machine inputs.
Claim 8
Dependent Claim
208 words
A programmable state machine comprising: a plurality of clocked macrocells, each having a state register, said macrocells having a cascade input and a cascade output, said cascade output being responsive to the state of said state register in the respective said macrocell, said macrocells having the cascade output of one macrocell coupled to the cascade input of the next macrocell, each of said macrocells being programmably responsive to a condition input and the cascade input to control the state of the state register therein; a programmable AND gate input array coupled to said macrocells for logically combining state machine inputs to provide said condition inputs to said macrocell; a programmable OR gate output array coupled to said macrocells and responsive to the state of said state register in each said macrocell to provide state machine outputs responsive to the state machine inputs and the programming of said state machine, and, feedback means for feeding the state register outputs from said macrocells back to said input array, whereby said input array may be programmed to provide as condition inputs to any of said macrocells, the state register output of any one or more of said macrocells alone or in combination with the logical combination of the state machine inputs.
Claim 9
Dependent Claim
53 words
The programmable state machine of claim 6 wherein said programmable input array includes inverters so as to be responsive to the state machine inputs and the inverse thereof to provide as the condition inputs to said macrocells, the AND of an AND and an OR of the state machine inputs and current state.
Claim 10
Dependent Claim
71 words
The programmable state machine of claim 7 wherein each macrocell is programmable to execute one of at least three operations, including (i) a start operation responsive to an input to set the respective state register for one clock cycle, (ii) a toggle operation responsive to an input to invert the state of the respective state register, and (iii) a terminate operation responsive to an input to reset the respective state register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |