US4786829A
Expired / Lapsed
US
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Latched fedback memory finite-state-engine
Assignee: National Semiconductor Corp
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Filing: 1987-02-24
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Granted: 1988-11-22
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Expires: 2007-02-24
Abstract
Abstract Disclosed herein is a simple latched-fedback-memory finite-state-engine that produces an inherently stable output upon the receipt of a clock signal, that is synchronously or asynchronously generated. The finite-state-engine comprises at least three latches and a function module, wherein the output of one latch is used as an input for the function module and a previous output of the function module is re-entered as an input into the function module.
Inventors
- 👤 John H. Letcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
110 words
A finite-state-engine comprising: a first latch means having as an input a data set X for producing an output X 1 upon the receipt of a clock signal; function module means for storing at least one finite-state equation and having as an input X 1 and Y 1 , and as an output Y 1 ' and Y 2 '; a second latch means having as an input Y 1 ' for producing an output Y 1 upon the receipt of the clock signal; and a third latch means having as an input Y 2 ' for producing an output Y 2 upon the receipt of a following clock signal.
Claim 2
Dependent Claim
110 words
A finite-state-engine comprising: a first latch means having as an input a data set X for producing an output X 1 upon the receipt of a clock signal; function module means for storing at least one finite-state equation and having as an input X 1 and Y 1 , and as an output Y 1 ' and Y 2 '; a second latch means having as an input Y 1 ' for producing an output Y 1 upon the receipt of the clock signal; and a third latch means having as an input Y 2 ' for producing an output Y 2 upon the receipt of a following clock signal.
Claim 3
Dependent Claim
17 words
The finite-state-engine of claim 1 wherein one or more of the latch means comprises a shift register.
Claim 4
Dependent Claim
18 words
The finite-state-engine of claim 2 wherein one or more of the latch means comprises a parallel-entry shift register.
Claim 5
Dependent Claim
16 words
The finite-state-engine of claim 1 wherein the function module means comprises a programmable solid-state memory device.
Claim 6
Dependent Claim
25 words
The finite-state engine of claim 4 wherein the function module means is selected from the group consisting of RAM, PROM, EPROM, PLA, PAL and HAL.
Claim 7
Dependent Claim
51 words
The finite-state-engine of claim 1 wherein the at least one finite state equation is in the form of Y:=F (X, Y) where X is a state vector, := is replaced by, F is a Boolean function of X and Y of a preceding time state, and Y is an output vector.
Claim 8
Dependent Claim
12 words
The finite-state-engine of claim 1 wherein the clock signal is synchronously generated.
Claim 9
Dependent Claim
12 words
The finite-state-engine of claim 1 wherein the clock signal is asynchronously generated.
Claim 10
Dependent Claim
35 words
The finite-state-engine of claim 1 wherein a time lapse between two falling edges of the clock signal is greater than a total internal time delay of the first latch means and the function module means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-22 | 1992-05-23 | 1992-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-22 | 1996-05-23 | 1996-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-22 | 2000-05-23 | 2000-11-22 | $7700.00 | Window Closed / Lapsed |