US4717844A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic array circuit with a decreased number of product terms
Assignee: Hitachi Ltd
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Filing: 1986-02-27
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Granted: 1988-01-05
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Expires: 2006-02-27
Abstract
Abstract A programmable logic array circuit which assumes terms which are not implicants to be DON'T CARE terms, and which produces a logic function having decreased number of product terms; and which has a logic function which eliminates the terms that have been regarded to be DON'T CARE terms.
Inventors
- 👤 Kazumasa Shima
- 👤 Syunpei Kawasaki
- 👤 Takashige Kubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
A programmable logic array circuit comprising: a first AND array, a first OR array, a second AND array, and a second OR array, wherein the output of the first AND array is connected to the input of the first OR array, the output of the second AND array is connected to the input of the second OR array, the input of the first AND array is connected to the input of the second AND array; and logic circuit means responsive to the output of the second OR array having a positive logic value for causing the output of the first AND array or the first OR array to have a negative logic value.
Claim 2
Dependent Claim
113 words
A programmable logic array circuit comprising: a first AND array, a first OR array, a second AND array, and a second OR array, wherein the output of the first AND array is connected to the input of the first OR array, the output of the second AND array is connected to the input of the second OR array, the input of the first AND array is connected to the input of the second AND array; and logic circuit means responsive to the output of the second OR array having a positive logic value for causing the output of the first AND array or the first OR array to have a negative logic value.
Claim 3
Dependent Claim
111 words
A programmable logic array circuit according to claim 1, wherein the logic circuit means which causes the output of the first AND array to be of a negative logic value when the output of the second OR array contains a positive logic value, comprises: a NOT gate with its input being connected to the output of the second OR array; an input line added to the first AND array; a signal line which connects the output of said NOT gate to said input line; and a gate element which causes the logic value of said input line to be negative when said output of said NOT gate assumes a negative value.
Claim 4
Dependent Claim
102 words
A programmable logic array circuit, characterized in that, the logic of said logic array is separated into a first term set and a second term set, the terms of each of said term sets being disjointed with respect to the terms of the other term set, logic array circuit comprising: a first logic circuit constituted in accordance with said first term set having at least one term in common with said second term set as a DON'T CARE term; and a second logic circuit which subtracts said DON'T CARE term from said first and second term sets of said first logic circuit".
Claim 5
Dependent Claim
102 words
A programmable logic array circuit, characterized in that, the logic of said logic array is separated into a first term set and a second term set, the terms of each of said term sets being disjointed with respect to the terms of the other term set, logic array circuit comprising: a first logic circuit constituted in accordance with said first term set having at least one term in common with said second term set as a DON'T CARE term; and a second logic circuit which subtracts said DON'T CARE term from said first and second term sets of said first logic circuit".
Claim 6
Dependent Claim
20 words
A programmable logic array circuit according to claim 3, wherein said first and second term sets are product term sets.
Claim 7
Dependent Claim
24 words
A programmable logic array circuit according to claim 3 or 4, wherein said first and second logic circuits are constituted by programmable logic arrays.
References Cited (Backward Citations)
US4041459A
Cited
US4336468A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-04 | 1991-07-06 | 1992-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-04 | 1995-07-06 | 1996-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-04 | 1999-07-06 | 2000-01-05 | $7700.00 | Window Closed / Lapsed |