US4910508A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Matrix logic circuit network suitable for large-scale integration
Assignee: Toshiba Corp
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Filing: 1985-12-16
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Granted: 1990-03-20
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Expires: 2005-12-16
Abstract
Abstract A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm, direct connection points of the input and output lines to which the same signals are allotted and connecting elements forming logic gates located at given intersections of the input and output lines are arranged within a diagonal area with a limited width, which extends along a diagonal line of the matrix.
Inventors
- 👤 Isamu Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:59
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5057; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17736; H03K19/1778
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
218 words
A matrix logic circuit network comprising: a plurality of logic gates having input and output lines and active elements, said plurality of logic gates being arranged such that an output line of one logic gate is connected to an input line of another succeeding logic gate, and said input and output lines of said logic gates being arranged respectively as a matrix array of column lines and row lines; and direct connection points at which corresponding input and output lines, to which an identical signal is applied, are directly connected to each other at intersections of said input and output lines within said matrix array so that an output line of one logic gate is directly connected to an input line of another succeeding logic gate of said logic gates; said active elements being arranged at given intersections of said input and output lines of said matrix array to form said logic gates; said input and output lines of said matrix array, said direct connection points and said active elements being arranged solely within a diagonal area smaller than the entire matrix having a given width which extends along a diagonal line of said matrix array; said diagonal area being divided into a plurality of sub-areas in parallel with a first one of said input and output lines.
Claim 2
Dependent Claim
218 words
A matrix logic circuit network comprising: a plurality of logic gates having input and output lines and active elements, said plurality of logic gates being arranged such that an output line of one logic gate is connected to an input line of another succeeding logic gate, and said input and output lines of said logic gates being arranged respectively as a matrix array of column lines and row lines; and direct connection points at which corresponding input and output lines, to which an identical signal is applied, are directly connected to each other at intersections of said input and output lines within said matrix array so that an output line of one logic gate is directly connected to an input line of another succeeding logic gate of said logic gates; said active elements being arranged at given intersections of said input and output lines of said matrix array to form said logic gates; said input and output lines of said matrix array, said direct connection points and said active elements being arranged solely within a diagonal area smaller than the entire matrix having a given width which extends along a diagonal line of said matrix array; said diagonal area being divided into a plurality of sub-areas in parallel with a first one of said input and output lines.
Claim 3
Dependent Claim
20 words
A matrix logic circuit network according to claim 1 characterized in that said logic gates each have a NAND/NOR function.
Claim 4
Dependent Claim
32 words
A matrix circuit network according to claim 1, in which said sub-areas are arranged side-by-side to partially overlap one another with respect to a second one of said input and output lines.
Claim 5
Dependent Claim
27 words
A matrix logic circuit network according to claim 3 characterized in that first and second lines are said output and input lines of said logic gates, respectively.
Claim 6
Dependent Claim
18 words
A matrix logic circuit network according to claim 1 characterized in that said connecting elements are MOS transistors.
Claim 7
Dependent Claim
17 words
A matrix logic circuit network according claim 1 characterized in that said connecting elements are bipolar transistors.
Claim 8
Dependent Claim
43 words
A matrix logic circuit network according to claim 1 characterized in that said connecting elements are provided at the respective intersections of said input and output lines, and circuit means is provided for selectively setting said connecting means in an electrical connection state.
Claim 9
Dependent Claim
219 words
A matrix logic circuit network comprising: a plurality of logic gates having input and output lines and active elements, said plurality of logic gates being arranged each that an output line of one logic gate is connected to an input line of another succeeding logic gate, and said input and output lines of said logic gates being arranged respectively as a matrix array of column lines and row line; and direct connection points at which corresponding input and output lines, to which an identical signal is applied, are directly connected to each other within said matrix array so that an output line of one logic gate is directly connected to an input line of another succeeding logic gate o said logic gates; said active elements being arranged at given intersections of said input and output lines of said matrix array to form said logic gates; said direct connection points and said active elements being arranged solely within a diagonal area smaller than the entire matrix extending along a diagonal line of said matrix array, said diagonal area being divided into a plurality of sub-areas in parallel with a first one of said input and output lines, and said sub-areas being arranged side-by-side to partially overlap one another with respect to a second one of said input and output lines.
Claim 10
Dependent Claim
219 words
A matrix logic circuit network comprising: a plurality of logic gates having input and output lines and active elements, said plurality of logic gates being arranged each that an output line of one logic gate is connected to an input line of another succeeding logic gate, and said input and output lines of said logic gates being arranged respectively as a matrix array of column lines and row line; and direct connection points at which corresponding input and output lines, to which an identical signal is applied, are directly connected to each other within said matrix array so that an output line of one logic gate is directly connected to an input line of another succeeding logic gate o said logic gates; said active elements being arranged at given intersections of said input and output lines of said matrix array to form said logic gates; said direct connection points and said active elements being arranged solely within a diagonal area smaller than the entire matrix extending along a diagonal line of said matrix array, said diagonal area being divided into a plurality of sub-areas in parallel with a first one of said input and output lines, and said sub-areas being arranged side-by-side to partially overlap one another with respect to a second one of said input and output lines.
References Cited (Backward Citations)
US3816725A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-03-19 | 1993-09-18 | 1994-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-03-19 | 1997-09-18 | 1998-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-03-19 | 2001-09-18 | 2002-03-20 | $7700.00 | Window Closed / Lapsed |