Matrix logic circuit network suitable for large-scale integration

Claim 2

A matrix logic circuit network comprising: a plurality of logic gates having input and output lines and active elements, said plurality of logic gates being arranged such that an output line of one logic gate is connected to an input line of another succeeding logic gate, and said input and output lines of said logic gates being arranged respectively as a matrix array of column lines and row lines; and direct connection points at which corresponding input and output lines, to which an identical signal is applied, are directly connected to each other at intersections of said input and output lines within said matrix array so that an output line of one logic gate is directly connected to an input line of another succeeding logic gate of said logic gates; said active elements being arranged at given intersections of said input and output lines of said matrix array to form said logic gates; said input and output lines of said matrix array, said direct connection points and said active elements being arranged solely within a diagonal area smaller than the entire matrix having a given width which extends along a diagonal line of said matrix array; said diagonal area being divided into a plurality of sub-areas in parallel with a first one of said input and output lines.

Claim 3

A matrix logic circuit network according to claim 1 characterized in that said logic gates each have a NAND/NOR function.

Claim 4

A matrix circuit network according to claim 1, in which said sub-areas are arranged side-by-side to partially overlap one another with respect to a second one of said input and output lines.

Claim 5

A matrix logic circuit network according to claim 3 characterized in that first and second lines are said output and input lines of said logic gates, respectively.

Claim 6

A matrix logic circuit network according to claim 1 characterized in that said connecting elements are MOS transistors.

Claim 7

A matrix logic circuit network according claim 1 characterized in that said connecting elements are bipolar transistors.

Claim 8

A matrix logic circuit network according to claim 1 characterized in that said connecting elements are provided at the respective intersections of said input and output lines, and circuit means is provided for selectively setting said connecting means in an electrical connection state.

Claim 9

A matrix logic circuit network comprising: a plurality of logic gates having input and output lines and active elements, said plurality of logic gates being arranged each that an output line of one logic gate is connected to an input line of another succeeding logic gate, and said input and output lines of said logic gates being arranged respectively as a matrix array of column lines and row line; and direct connection points at which corresponding input and output lines, to which an identical signal is applied, are directly connected to each other within said matrix array so that an output line of one logic gate is directly connected to an input line of another succeeding logic gate o said logic gates; said active elements being arranged at given intersections of said input and output lines of said matrix array to form said logic gates; said direct connection points and said active elements being arranged solely within a diagonal area smaller than the entire matrix extending along a diagonal line of said matrix array, said diagonal area being divided into a plurality of sub-areas in parallel with a first one of said input and output lines, and said sub-areas being arranged side-by-side to partially overlap one another with respect to a second one of said input and output lines.

Claim 10

A matrix logic circuit network comprising: a plurality of logic gates having input and output lines and active elements, said plurality of logic gates being arranged each that an output line of one logic gate is connected to an input line of another succeeding logic gate, and said input and output lines of said logic gates being arranged respectively as a matrix array of column lines and row line; and direct connection points at which corresponding input and output lines, to which an identical signal is applied, are directly connected to each other within said matrix array so that an output line of one logic gate is directly connected to an input line of another succeeding logic gate o said logic gates; said active elements being arranged at given intersections of said input and output lines of said matrix array to form said logic gates; said direct connection points and said active elements being arranged solely within a diagonal area smaller than the entire matrix extending along a diagonal line of said matrix array, said diagonal area being divided into a plurality of sub-areas in parallel with a first one of said input and output lines, and said sub-areas being arranged side-by-side to partially overlap one another with respect to a second one of said input and output lines.