US5877050A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals
Assignee: Advanced Micro Devices Inc
•
Filing: 1996-09-03
•
Granted: 1999-03-02
•
Expires: 2016-09-03
Abstract
Abstract A method of making N-channel and P-channel IGFETs is disclosed. The method includes, in sequence, the steps of partially doping a first source and a first drain in a first active region of a semiconductor substrate, applying a first tube anneal while a second active region of the semiconductor substrate is devoid of source/drain doping, partially doping a second source and a second drain in the second active region, applying a second tube anneal, fully doping the first source and the first drain, applying a first rapid thermal anneal, fully doping the second source and the second drain, and applying a second rapid thermal anneal. Advantageously, the first and second tube anneals provide control over the channel junction locations, and the first and second rapid thermal anneals provide rapid drive-in for subsequent source/drain doping spaced from the channel junctions.
Inventors
- 👤 Mark I. Gardner
- 👤 Derick J. Wristers
- 👤 H. Jim Fulford, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:53
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
104 words
A method of making N-channel and P-channel IGFETs, comprising the following steps in the sequence set forth: partially doping a first source and a first drain in a first active region of a semiconductor substrate; applying a first tube anneal while a second active region of the semiconductor substrate is devoid of source/drain doping; partially doping a second source and a second drain in the second active region; applying a second tube anneal; fully doping the first source and the first drain; applying a first rapid thermal anneal; fully doping the second source and the second drain; and applying a second rapid thermal anneal.
Claim 2
Independent Claim
104 words
A method of making N-channel and P-channel IGFETs, comprising the following steps in the sequence set forth: partially doping a first source and a first drain in a first active region of a semiconductor substrate; applying a first tube anneal while a second active region of the semiconductor substrate is devoid of source/drain doping; partially doping a second source and a second drain in the second active region; applying a second tube anneal; fully doping the first source and the first drain; applying a first rapid thermal anneal; fully doping the second source and the second drain; and applying a second rapid thermal anneal.
Claim 3
Dependent Claim
53 words
The method of claim 1, wherein: partially doping the first source and the first drain includes implanting first lightly doped source and drain regions into the first active region; and partially doping the second source and the second drain includes implanting second lightly doped source and drain regions into the second active region.
Claim 4
Dependent Claim
83 words
The method of claim 2, wherein: partially doping the first source and the first drain includes converting at least a portion of the first lightly doped source region into a first heavily doped source region; and fully doping the first source and the first drain includes converting at least a portion of the first heavily doped source region into a first ultra-heavily doped source region, and converting a portion of the first lightly doped drain region into a first heavily doped drain region.
Claim 5
Dependent Claim
41 words
The method of claim 3, wherein partially doping the first source and the first drain includes converting substantially all of the first lightly doped source region into the first heavily doped source region without doping the first lightly doped drain region.
Claim 6
Dependent Claim
33 words
The method of claim 3, wherein fully doping the first source and the first drain includes converting substantially all of the first heavily doped source region into the first ultra-heavily doped source region.
Claim 7
Dependent Claim
51 words
The method of claim 3, wherein fully doping the second source and the second drain includes converting a portion of the second lightly doped source region into a second heavily doped source region, and converting a portion of the second lightly doped drain region into a second heavily doped drain region.
Claim 8
Dependent Claim
29 words
The method of claim 1, wherein the N-channel IGFET includes the first source and the first drain, and the P-channel IGFET includes the second source and the second drain.
Claim 9
Dependent Claim
14 words
The method of claim 7, wherein the N-channel and P-channel IGFETs are both symmetrical.
Claim 10
Dependent Claim
14 words
The method of claim 7, wherein the N-channel and P-channel IGFETs are both asymmetrical.
Claim 11
Dependent Claim
17 words
The method of claim 7, wherein the N-channel IGFET is asymmetrical and the P-channel IGFET is symmetrical.
Claim 12
Dependent Claim
63 words
The method of claim 1, wherein: the first tube anneal is performed at a first temperature; the second tube anneal is performed at a second temperature; the first rapid thermal anneal is performed at a third temperature; the second rapid thermal anneal is performed at a fourth temperature; the first temperature exceeds the second temperature, and the third temperature exceeds the fourth temperature.
Claim 13
Dependent Claim
31 words
The method of claim 11, wherein: the first temperature exceeds the second temperature by at least 50° C.; and the third temperature exceeds the fourth temperature by at least 50° C.
Claim 14
Dependent Claim
31 words
The method of claim 11, wherein: the first temperature is in the range of 825° to 875° C.; and the second temperature is in the range of 775° to 825° C.
Claim 15
Dependent Claim
31 words
The method of claim 11, wherein the third temperature is in the range of 950° to 1050° C.; and the fourth temperature is in the range of 800° to 1000° C.
Claim 16
Dependent Claim
59 words
The method of claim 11, wherein: the first temperature is maintained in the range of 30 to 75 minutes; the second temperature is maintained in the range of 30 to 75 minutes; the third temperature is maintained in the range of 10 to 60 seconds; and the fourth temperature is maintained in the range of 10 to 60 seconds.
Claim 17
Dependent Claim
21 words
The method of claim 1, wherein the first and second active regions are adjacent to an isolation region in the substrate.
Claim 18
Dependent Claim
15 words
The method of claim 1, wherein the N-channel and P-channel IGFETs provide an inverter circuit.
Claim 19
Independent Claim
242 words
A method of making N-channel and P-channel IGFETs, comprising the following steps in the sequence set forth: providing a semiconductor substrate with a P-type active region and an N-type active region; providing a first gate with first and second opposing sidewalls over the P-type active region, and a second gate with third and fourth opposing sidewalls over the N-type active region; implanting a first N-type dopant to provide lightly doped N-type source and drain regions in the P-type active region; applying a first tube anneal at a first temperature to drive-in the first N-type dopant while the N-type active region is devoid of source/drain doping; implanting a first P-type dopant to provide lightly doped P-type source and drain regions in the N-type active region; applying a second tube anneal at a second temperature, less than the first temperature, to drive-in the first P-type dopant; implanting a second N-type dopant to provide a heavily doped N-type drain region in the P-type active region; applying a first rapid thermal anneal at a third temperature to drive-in the second N-type dopant and form an N-type source and drain in the P-type active region; implanting a second P-type dopant to provide a heavily doped P-type drain region in the N-type active region; and applying a second rapid thermal anneal at a fourth temperature, less than the third temperature, to drive-in the second P-type dopant and form a P-type source and drain in the N-type active region.
Claim 20
Independent Claim
242 words
A method of making N-channel and P-channel IGFETs, comprising the following steps in the sequence set forth: providing a semiconductor substrate with a P-type active region and an N-type active region; providing a first gate with first and second opposing sidewalls over the P-type active region, and a second gate with third and fourth opposing sidewalls over the N-type active region; implanting a first N-type dopant to provide lightly doped N-type source and drain regions in the P-type active region; applying a first tube anneal at a first temperature to drive-in the first N-type dopant while the N-type active region is devoid of source/drain doping; implanting a first P-type dopant to provide lightly doped P-type source and drain regions in the N-type active region; applying a second tube anneal at a second temperature, less than the first temperature, to drive-in the first P-type dopant; implanting a second N-type dopant to provide a heavily doped N-type drain region in the P-type active region; applying a first rapid thermal anneal at a third temperature to drive-in the second N-type dopant and form an N-type source and drain in the P-type active region; implanting a second P-type dopant to provide a heavily doped P-type drain region in the N-type active region; and applying a second rapid thermal anneal at a fourth temperature, less than the third temperature, to drive-in the second P-type dopant and form a P-type source and drain in the N-type active region.
Claim 21
Dependent Claim
41 words
The method of claim 18, wherein: implanting the second N-type dopant provides a heavily doped N-type source region in the P-type active area; and implanting the second P-type dopant provides a heavily doped P-type source region in the N-type active area.
Claim 22
Dependent Claim
114 words
The method of claim 18, including: implanting a third N-type dopant to convert substantially all of the lightly doped N-type source region into a heavily doped N-type source region without doping the lightly doped N-type drain region; applying the first tube anneal to drive-in the first and third N-type dopants; forming first and second spacers adjacent to the first and second sidewalls, respectively; and implanting the second N-type dopant to convert a portion of the heavily doped N-type source region outside the first spacer into an ultra-heavily doped N-type source region, and to convert a portion of the lightly doped N-type drain region outside the second spacer into a heavily doped N-type drain region.
Claim 23
Dependent Claim
82 words
The method of claim 20, wherein: the N-type source includes the heavily doped and ultra-heavily doped N-type source regions, the heavily doped N-type source region provides a first channel junction and the ultra-heavily doped N-type source region is spaced from the first channel junction; and the N-type drain includes the lightly and heavily doped N-type drain regions, the lightly doped N-type drain region provides a second channel junction and the heavily doped N-type drain region is spaced from the second channel junction.
Claim 24
Dependent Claim
70 words
The method of claim 21, including: forming third and fourth spacers adjacent to the third and fourth sidewalls, respectively; and implanting the second P-type dopant to convert a portion of the lightly doped P-type source region outside the third spacer into a heavily doped P-type source region, and to convert a portion of the lightly doped P-type drain region outside the fourth spacer into the heavily doped P-type drain region.
Claim 25
Dependent Claim
31 words
The method of claim 18, wherein: the first temperature exceeds the second temperature by at least 50° C.; and the third temperature exceeds the fourth temperature by at least 50° C.
Claim 26
Dependent Claim
98 words
The method of claim 18, wherein: the first temperature is in the range of 825° to 875° C. and is maintained in the range of 30 to 75 minutes; the second temperature is in the range of 775° to 825° C. is maintained in the range of 30 to 75 minutes; the third temperature is in the range of 950° to 1050° C. and is maintained in the range of 10 to 60 seconds; and the fourth temperature is in the range of 800° to 1000° C. and is maintained in the range of 10 to 60 seconds.
Claim 27
Dependent Claim
24 words
The method of claim 18, wherein the N-type active region and the P-type active region are adjacent to an isolation region in the substrate.
Claim 28
Dependent Claim
15 words
The method of claim 18, wherein the N-channel and P-channel IGFETs provide an inverter circuit.
Claim 29
Dependent Claim
46 words
The method of claim 18, wherein: the first and second N-type dopants are each selected from the group consisting of arsenic, phosphorus, and combinations thereof, and the first and second P-type dopants are each selected from the group consisting of boron, boron species and combinations thereof.
Claim 30
Independent Claim
529 words
A method of making an asymmetrical N-channel IGFET and a symmetrical P-channel IGFET using two tube anneals and two rapid thermal anneals, comprising the steps of: providing a semiconductor substrate with a P-type active region and an N-type active region; forming a first gate insulator on the P-type active region; forming a second gate insulator on the N-type active region; forming a first gate with first and second opposing sidewalls on the first gate insulator; forming a second gate with third and fourth opposing sidewalls on the second gate insulator; then implanting a first N-type dopant to form lightly doped N-type source and drain regions in the P-type active region and substantially aligned with the first and second sidewalls, respectively; implanting a second N-type dopant to convert substantially all of the lightly doped N-type source region into a heavily doped N-type source region without doping the lightly doped N-type drain region; then applying a first tube anneal at a first temperature to drive-in the first and second N-type dopants while the N-type active region is devoid of source/drain doping; then implanting a first P-type dopant to form lightly doped P-type source and drain regions in the N-type active region and substantially aligned with the third and fourth sidewalls, respectively; then applying a second tube anneal at a second temperature, less than the first temperature, to drive-in the first P-type dopant; forming first, second, third and fourth spacers adjacent to the first, second, third and fourth sidewalls, respectively; then implanting a third N-type dopant to convert a portion of the heavily doped N-type source region outside the first spacer into an ultra-heavily doped N-type source region without doping a portion of the heavily doped N-type source region beneath the first spacer, and to convert a portion of the lightly doped N-type drain region outside the second spacer into a heavily doped N-type drain region without doping a portion of the lightly doped N-type drain region beneath the second spacer; then applying a first rapid thermal anneal at a third temperature to drive-in the third N-type dopant and form an N-type source and drain in the P-type active region, wherein the N-type source includes the heavily doped and ultra-heavily doped N-type source regions, and the N-type drain includes the lightly doped and heavily doped N-type drain regions; then implanting a second P-type dopant to convert a portion of the lightly doped P-type source region outside the third spacer into a heavily doped P-type source region without doping a portion of the lightly doped P-type source region beneath the third spacer, and to convert a portion of the lightly doped P-type drain region outside the fourth spacer into a heavily doped P-type drain region without doping a portion of the lightly doped P-type drain region beneath the fourth spacer; and then applying a second rapid thermal anneal at a fourth temperature, less than the third temperature, to drive-in the second P-type dopant and form a P-type source and drain in the N-type active region, wherein the P-type source includes the lightly doped and heavily doped P-type source regions, and the P-type drain includes the lightly doped and heavily doped P-type drain regions.
Claim 31
Independent Claim
529 words
A method of making an asymmetrical N-channel IGFET and a symmetrical P-channel IGFET using two tube anneals and two rapid thermal anneals, comprising the steps of: providing a semiconductor substrate with a P-type active region and an N-type active region; forming a first gate insulator on the P-type active region; forming a second gate insulator on the N-type active region; forming a first gate with first and second opposing sidewalls on the first gate insulator; forming a second gate with third and fourth opposing sidewalls on the second gate insulator; then implanting a first N-type dopant to form lightly doped N-type source and drain regions in the P-type active region and substantially aligned with the first and second sidewalls, respectively; implanting a second N-type dopant to convert substantially all of the lightly doped N-type source region into a heavily doped N-type source region without doping the lightly doped N-type drain region; then applying a first tube anneal at a first temperature to drive-in the first and second N-type dopants while the N-type active region is devoid of source/drain doping; then implanting a first P-type dopant to form lightly doped P-type source and drain regions in the N-type active region and substantially aligned with the third and fourth sidewalls, respectively; then applying a second tube anneal at a second temperature, less than the first temperature, to drive-in the first P-type dopant; forming first, second, third and fourth spacers adjacent to the first, second, third and fourth sidewalls, respectively; then implanting a third N-type dopant to convert a portion of the heavily doped N-type source region outside the first spacer into an ultra-heavily doped N-type source region without doping a portion of the heavily doped N-type source region beneath the first spacer, and to convert a portion of the lightly doped N-type drain region outside the second spacer into a heavily doped N-type drain region without doping a portion of the lightly doped N-type drain region beneath the second spacer; then applying a first rapid thermal anneal at a third temperature to drive-in the third N-type dopant and form an N-type source and drain in the P-type active region, wherein the N-type source includes the heavily doped and ultra-heavily doped N-type source regions, and the N-type drain includes the lightly doped and heavily doped N-type drain regions; then implanting a second P-type dopant to convert a portion of the lightly doped P-type source region outside the third spacer into a heavily doped P-type source region without doping a portion of the lightly doped P-type source region beneath the third spacer, and to convert a portion of the lightly doped P-type drain region outside the fourth spacer into a heavily doped P-type drain region without doping a portion of the lightly doped P-type drain region beneath the fourth spacer; and then applying a second rapid thermal anneal at a fourth temperature, less than the third temperature, to drive-in the second P-type dopant and form a P-type source and drain in the N-type active region, wherein the P-type source includes the lightly doped and heavily doped P-type source regions, and the P-type drain includes the lightly doped and heavily doped P-type drain regions.
Claim 32
Dependent Claim
57 words
The method of claim 28, wherein: a dopant concentration of the heavily doped N-type source and drain regions is at least 10 times that of the lightly doped N-type drain region; and a dopant concentration of the ultra-heavily doped N-type source region is at least 1.5 times that of the heavily doped N-type source and drain regions.
Claim 33
Dependent Claim
80 words
The method of claim 29, wherein: the dopant concentration of the lightly doped N-type drain region is in the range of about 1×10 17 to 5×10 18 atoms/cm 3 ; the dopant concentration of the heavily doped N-type source and drain regions is in the range of about 1×10 19 to 5×10 18 atoms/cm 3 ; and the dopant concentration of the ultra-heavily doped N-type source region is in the range about 1.5×10 19 to 1×10 21 atoms/cm 3 .
Claim 34
Dependent Claim
83 words
The method of claim 28, wherein: the heavily doped N-type source region provides a first channel junction spaced from the ultra-heavily doped N-type source region; the lightly doped N-type source region provides a second channel junction spaced from the heavily doped N-type drain region; the lightly doped P-type source region provides a third channel junction spaced from the heavily doped P-type source region; and the lightly doped P-type drain region provides a fourth channel junction spaced from the heavily doped P-type drain region.
Claim 35
Dependent Claim
32 words
The method of claim 28, wherein forming the first, second, third and fourth spacers includes depositing a blanket layer of silicon dioxide over the substrate, and then applying a reactive ion etch.
Claim 36
Dependent Claim
28 words
The method of claim 28, wherein the first and second gates are polysilicon, the first and second gate insulators are silicon dioxide, and the spacers are silicon dioxide.
References Cited (Backward Citations)
US4225875A
Cited
US4272881A
Cited
US4575920A
Cited
EP0160255A2
Cited
EP0186058A1
Cited
EP0187016A2
Cited
JPS61194777A
Cited
US5215936A
Cited
US4927777A
Cited
US5521417A
Cited
US5585658A
Cited
US4956311A
Cited
US5073514A
Cited
US5132753A
Cited
US5547885A
Cited
US5436482A
Cited
US5296398A
Cited
JPH04118762A
Cited
US5171700A
Cited
US5424234A
Cited
US5424229A
Cited
US5169796A
Cited
US5286664A
Cited
US5200358A
Cited
EP0575099A1
Cited
US5366915A
Cited
US5349225A
Cited
US5451807A
Cited
US5578509A
Cited
US5364807A
Cited
US5397715A
Cited
US5547888A
Cited
US5607869A
Cited
US5518940A
Cited
US5585293A
Cited
JPH0878672A
Cited
US5512503A
Cited
US5510279A
Cited
US5525552A
Cited
US5672531A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-01 | 2002-08-31 | 2003-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-01 | 2006-08-31 | 2007-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-01 | 2010-08-31 | 2011-03-02 | $7700.00 | Window Closed / Lapsed |