Process for fabricating self-aligned metal gate field effect transistors

Claim 1

A method for fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing two source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween; (b) providing a gate oxide overlaying the source/drain regions and the channel; (c) providing a metal gate overlying a first portion of the channel; (d) providing dopant ions in a second portion of the channel using he metal gate provided in said step (c) as a mask; and (e) activating the dopant ions provided in said step (d) by rapid thermal annealing at temperatures between approximately 400° C. and 650° C. for a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. or a time between approximately 10 minutes and 30 minutes to form a bridge region which is self-aligned with the metal gate and which extends one of the source/drain regions laterally into the channel.

Claim 2

A method for fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing two source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween; (b) providing a gate oxide overlaying the source/drain regions and the channel; (c) providing a metal gate overlying a first portion of the channel; (d) providing dopant ions in a second portion of the channel using he metal gate provided in said step (c) as a mask; and (e) activating the dopant ions provided in said step (d) by rapid thermal annealing at temperatures between approximately 400° C. and 650° C. for a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. or a time between approximately 10 minutes and 30 minutes to form a bridge region which is self-aligned with the metal gate and which extends one of the source/drain regions laterally into the channel.

Claim 13

A method of fabricating a metal gate field effect transistor in a substrate, comprising the step of: (a) providing two source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween, the channel having a length L; (b) providing a gate oxide overlying the source/drain regions and the channel; (c) provide in a metal gate overlying at least a first portion of the channel, the first portion of the channel having a length M, where M is approximately equal to or less than L; (d) implanting dopant ions in a second portion of the channel after said step (c); and (e) activating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500°0 C. and 550° C. for a time between approximately 5 seconds and approximately 45 seconds, and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a bridge which extends a source/drain region laterally into the second portion of the channel and which is elf-aligned with the metal gate.

Claim 14

A method of fabricating a metal gate field effect transistor in a substrate, comprising the step of: (a) providing two source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween, the channel having a length L; (b) providing a gate oxide overlying the source/drain regions and the channel; (c) provide in a metal gate overlying at least a first portion of the channel, the first portion of the channel having a length M, where M is approximately equal to or less than L; (d) implanting dopant ions in a second portion of the channel after said step (c); and (e) activating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500°0 C. and 550° C. for a time between approximately 5 seconds and approximately 45 seconds, and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a bridge which extends a source/drain region laterally into the second portion of the channel and which is elf-aligned with the metal gate.

Claim 16

A method of fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing tow source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween, the channel having a length L; (b) providing a gate oxide overlying the source/drain regions and the channel; (c) providing an aluminum gate overlying at least a portion of the channel, the aluminum gate having a length M, where M is approximately equal to or less than L; (d) providing dopant ions in a second portion o the channel using the aluminum gate as a mask; and (e) actuating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500° C. and 550° c. for a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a bridge which extends a source/drain region laterally into the second portion of the channel and which is self-aligned with the aluminum gate.

Claim 17

A method of fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing tow source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween, the channel having a length L; (b) providing a gate oxide overlying the source/drain regions and the channel; (c) providing an aluminum gate overlying at least a portion of the channel, the aluminum gate having a length M, where M is approximately equal to or less than L; (d) providing dopant ions in a second portion o the channel using the aluminum gate as a mask; and (e) actuating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500° C. and 550° c. for a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a bridge which extends a source/drain region laterally into the second portion of the channel and which is self-aligned with the aluminum gate.

Claim 19

A method of fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing a source and a drain region in the substrate, the source and rain regions being spaced apart to define a channel therebetween, the channel having a length L; (b) providing a gate oxide overlying the source/drain regions and he channel; (c) providing a metal gate overlying a first portion of the channel, the metal gate having a length M, where M is approximately L/2; (d) providing dopant ions in a second portion and a third portion of the channel using the metal gate as a mask; and (e) activating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500° C. and 550° c. or a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a first bridge in the second portion of the channel and to form a second bridge in the third portion of the channel, the first and second bridges being self-aligned with the metal gate.

Claim 20

A method of fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing a source and a drain region in the substrate, the source and rain regions being spaced apart to define a channel therebetween, the channel having a length L; (b) providing a gate oxide overlying the source/drain regions and he channel; (c) providing a metal gate overlying a first portion of the channel, the metal gate having a length M, where M is approximately L/2; (d) providing dopant ions in a second portion and a third portion of the channel using the metal gate as a mask; and (e) activating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500° C. and 550° c. or a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a first bridge in the second portion of the channel and to form a second bridge in the third portion of the channel, the first and second bridges being self-aligned with the metal gate.

Claim 22

A method of fabricating CMOS field effect transistor in a substrate having N-type conductivity and a surface, comprising the steps of: (a) growing a first oxide layer on the surface of the substrate; (b) removing a first selected portion of he first oxide layer corresponding to a region where a P-well is to be formed; (c) forming a P-well by implanting P-type dopant ions in the substrate using the portions of the first oxide layer remaining after said step (b) as a mask; (d) annealing the structures formed in said steps (a)-(c) to activate the dopant ions implanted in said step (c) and to grow a second oxide labyrinth regions where the first oxide layer was removed in said step (b); (e) implanting P-type dopant ions using the portions of the first oxide layer remaining after said step (d) and the second oxide layer as masks; (f) implanting N-type dopant using the portions of the first oxide layer remaining after said step (e) an eh second oxide layer as masks; (g) annealing the structures formed in said steps (a)-(f) to activate the dopants implanted in steps (e) and (f) to form P-type and N-type source/drain regions, the P-type source/drain regions being spaced apart to define a first channel of length L 1 therebetween and the N-type source/drain regions being spaced apart to define a second channel of length L 2 therebetween nd to grow a third oxide layer; (h) removing selected portions of the third oxide layer to expose portions of the surface of the substrate corresponding to the channel regions; (i) forming first and second aluminum gates, the aluminum gates overlying at least a portion of each of the respective first and second channel regions; (j) implanting in the first channel a P-type dopant using the first aluminum gate as a mask; (i) implanting in the second channel an N-type dopant using the second aluminum gate as a mask; and (l) activating the dopants implanted in steps (j) and (k) by rapid thermal annealing at a temperature between 500° C. and 550° C. for a time less than approximately 45 seconds to form a P-type bridge in the first channel and an N-type bridge in the second channel, each o the bridges extending a corresponding source/drain region laterally into the respective channel and being self-aligned with the respective aluminum gate.

Claim 23

A method of fabricating CMOS field effect transistor in a substrate having N-type conductivity and a surface, comprising the steps of: (a) growing a first oxide layer on the surface of the substrate; (b) removing a first selected portion of he first oxide layer corresponding to a region where a P-well is to be formed; (c) forming a P-well by implanting P-type dopant ions in the substrate using the portions of the first oxide layer remaining after said step (b) as a mask; (d) annealing the structures formed in said steps (a)-(c) to activate the dopant ions implanted in said step (c) and to grow a second oxide labyrinth regions where the first oxide layer was removed in said step (b); (e) implanting P-type dopant ions using the portions of the first oxide layer remaining after said step (d) and the second oxide layer as masks; (f) implanting N-type dopant using the portions of the first oxide layer remaining after said step (e) an eh second oxide layer as masks; (g) annealing the structures formed in said steps (a)-(f) to activate the dopants implanted in steps (e) and (f) to form P-type and N-type source/drain regions, the P-type source/drain regions being spaced apart to define a first channel of length L 1 therebetween and the N-type source/drain regions being spaced apart to define a second channel of length L 2 therebetween nd to grow a third oxide layer; (h) removing selected portions of the third oxide layer to expose portions of the surface of the substrate corresponding to the channel regions; (i) forming first and second aluminum gates, the aluminum gates overlying at least a portion of each of the respective first and second channel regions; (j) implanting in the first channel a P-type dopant using the first aluminum gate as a mask; (i) implanting in the second channel an N-type dopant using the second aluminum gate as a mask; and (l) activating the dopants implanted in steps (j) and (k) by rapid thermal annealing at a temperature between 500° C. and 550° C. for a time less than approximately 45 seconds to form a P-type bridge in the first channel and an N-type bridge in the second channel, each o the bridges extending a corresponding source/drain region laterally into the respective channel and being self-aligned with the respective aluminum gate.