Method for making improved Schottky-barrier gate gallium arsenide field effect devices

Claim 2

A process for fabricating a field effect transistor structure comprising the steps of: (a) providing a substrate of semi-insulating gallium arsenide; (b) forming a conducting channel on a surface of said substrate and defining a substrate-conducting channel interface; (c) establishing source and drain ohmic contacts on predetermined portions of a surface of said conducting channel, said portions defining a source region and a drain region respectively of said transistor structure; (d) controllably etching a cavity in said conducting channel between said source and drain ohmic contacts, said cavity having angled side walls and an adjoining bottom wall defining a trapezoidal shaped inverted mesa region and said angled side walls extending to said surface of said conducting channel at edges remote from said source and drain ohmic contacts, whereby a conducting channel region is formed that is relatively thin with respect to said source region and said drain region; and (e) depositing a gate electrode member primarily on said bottom wall of said cavity and with minimal contact with said side walls for minimizing parasitic coupling between said gate electrode member and said conducting channel.

Claim 3

A process for fabricating a field effect transistor structure comprising the steps of: (a) forming a conducting channel on a surface of a semi-insulating gallium arsenide substrate and defining a substrate-conducting channel interface; (b) establishing source and drain ohmic contacts on predetermined portions of a surface of said conducting channel, said portions defining a source region and drain region respectively of said transistor structure; (c) forming a resist mask on said conducting channel for the establishment of a gate region between said source and drain ohmic contacts; (d) forming a trapezoidal shaped inverted mesa cavity region in said conducting channel between said source and drain ohmic contacts by controllably etching through an opening in said resist mask for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to said substrate-conducting channel interface and angled side walls of said cavity region extending to said surface of said conducting channel at edges remote from said source and drain ohmic contacts, whereby a shallow conducting channel region of uniform thickness and relatively thin with respect to said source region and said drain region is formed; and (e) forming a Schottky-barrier gate electrode primarily on said flat horizontal lower surface using said resist mask to determine the location and size of said gate electrode.

Claim 4

A process for fabricating a field effect transistor structure comprising the steps of: (a) forming a conducting channel on a surface of a semi-insulating gallium arsenide substrate and defining a substrate-conducting channel interface; (b) establishing source and drain ohmic contacts on predetermined portions of a surface of said conducting channel, said portions defining a source region and drain region respectively of said transistor structure; (c) forming a resist mask on said conducting channel for the establishment of a gate region between said source and drain ohmic contacts; (d) forming a trapezoidal shaped inverted mesa cavity region in said conducting channel between said source and drain ohmic contacts by controllably etching through an opening in said resist mask for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to said substrate-conducting channel interface and angled side walls of said cavity region extending to said surface of said conducting channel at edges remote from said source and drain ohmic contacts, whereby a shallow conducting channel region of uniform thickness and relatively thin with respect to said source region and said drain region is formed; and (e) forming a Schottky-barrier gate electrode primarily on said flat horizontal lower surface using said resist mask to determine the location and size of said gate electrode.

Claim 5

A process as set forth in claim 2, wherein said gallium arsenide substrate has a bulk resistivity between 10 6 and 10 8 ohm-centimeters and has chromium as the dominant electrically active impurity.

Claim 6

A process as set forth in claim 3 wherein said conducting channel is formed by growing a thin epitaxial active layer on said substrate.

Claim 7

A process as set forth in claim 3 wherein said conducting channel is formed by implanting a suitable impurity in said substrate.

Claim 8

A process as set forth in claim 3 wherein said conducting channel is formed by growing a thin epitaxial active region and then implanting said epitaxial active region with suitable ions at controlled depths and dosages.

Claim 9

A process for fabricating a self-aligned Schottky-barrier gate gallium arsenide field effect transistor comprising the steps of: (a) providing a gallium arsenide substrate having a bulk resistivity between 10 6 and 10 8 ohm-centimeters and having chromium as the dominant electrically active impurity; (b) forming an N-type epitaxial layer having a chosen carrier concentration, and defining a substrate-epitaxial layer interface; (c) implanting an N-type impurity in said epitaxial layer thereby increasing the conductivity of said layer; (d) forming a diffusion barrier layer on the surface of said N-type epitaxial layer subsequent to the N-type implantation thereof whereby the stoichiometry of said surface is preserved; (e) annealing said structure at a predetermined elevated temperature sufficient to electrically activate said N-type ions implanted therein and to anneal out substantial amounts of ion implantation damage, whereby carrier mobilities in excess of 3,000 cm 2 /volt-second may be obtained in a layer of substantially uniform thickness; (f) establishing source and drain regions on said implanted epitaxial layer and respective source and drain electrodes on said regions after first making the necessary openings on said barrier layer, and subsequently removing said barrier layer through a chemical etch; (g) forming a resist mask on said surface of said implanted epitaxial layer for the establishment of a gate region between said source and drain electrodes; (h) forming a trapezoidal shaped inverted mesa cavity region in said implanted epitaxial layer between said source and drain electrodes by applying a preferential chemical etchant for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to said substrate-epitaxial layer interface and angled side walls of said cavity region extending to said surface of said implanted epitaxial layer at edges remote from said source and drain electrodes, whereby a shallow conducting channel region of uniform thickness, relatively thin with respect to said source and drain regions, and relatively close to said source region is formed; and (i) forming a Schottky-barrier gate primarily on said shallow conducting channel.

Claim 10

A process for fabricating a self-aligned Schottky-barrier gate gallium arsenide field effect transistor comprising the steps of: (a) providing a gallium arsenide substrate having a bulk resistivity between 10 6 and 10 8 ohm-centimeters and having chromium as the dominant electrically active impurity; (b) forming an N-type epitaxial layer having a chosen carrier concentration, and defining a substrate-epitaxial layer interface; (c) implanting an N-type impurity in said epitaxial layer thereby increasing the conductivity of said layer; (d) forming a diffusion barrier layer on the surface of said N-type epitaxial layer subsequent to the N-type implantation thereof whereby the stoichiometry of said surface is preserved; (e) annealing said structure at a predetermined elevated temperature sufficient to electrically activate said N-type ions implanted therein and to anneal out substantial amounts of ion implantation damage, whereby carrier mobilities in excess of 3,000 cm 2 /volt-second may be obtained in a layer of substantially uniform thickness; (f) establishing source and drain regions on said implanted epitaxial layer and respective source and drain electrodes on said regions after first making the necessary openings on said barrier layer, and subsequently removing said barrier layer through a chemical etch; (g) forming a resist mask on said surface of said implanted epitaxial layer for the establishment of a gate region between said source and drain electrodes; (h) forming a trapezoidal shaped inverted mesa cavity region in said implanted epitaxial layer between said source and drain electrodes by applying a preferential chemical etchant for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to said substrate-epitaxial layer interface and angled side walls of said cavity region extending to said surface of said implanted epitaxial layer at edges remote from said source and drain electrodes, whereby a shallow conducting channel region of uniform thickness, relatively thin with respect to said source and drain regions, and relatively close to said source region is formed; and (i) forming a Schottky-barrier gate primarily on said shallow conducting channel.

Claim 11

A process as set forth in claim 7 wherein: (a) said N-type epitaxial layer has a thickness ranging between 0.5 and 0.6 μm; and (b) said N-type epitaxial layer is implanted to a depth of approximately 0.2 μm with sulphur whereby the conductivity of said conducting channel is substantially enhanced.

Claim 12

A process as set forth in claim 7 wherein said barrier layer formed on said substrate prior to annealing is removed after said annealing and replaced with a new barrier layer.

Claim 13

The process set forth in claim 7 wherein: (a) said gallium arsenide substrate has a <100> crystallographic orientation; and (b) said preferential chemical etchant comprises 970 milliliters (ml) of water, 20 ml of ammonium hydroxide (NH 4 OH), and 7 ml of 30% hydrogen peroxide (H 2 O 2 ).

Claim 14

In a method for fabricating a gallium arsenide Schottky-barrier gate field effect transistor including the steps of forming a conducting channel on a surface of a semi-insulating gallium arsenide substrate, establishing source and drain ohmic contacts on predetermined portions of a surface of said conducting channel and thereby defining source and drain regions respectively, the improvement which comprises: (a) forming a resist etching mask on said conducting channel having an opening located between said source and drain contacts and closer to said source contact than to said drain contact; (b) forming a trapezoidal shaped inverted mesa cavity region in said conducting channel between said source and drain contacts and closer to said source contact than to said drain contact, by applying a preferential chemical etchant through said opening in said resist mask for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to the interface between said substrate and said conducting channel and angled said walls of said cavity region extending to said surface of said conducting channel at edges remote from said source and drain contacts, whereby a shallow conducting channel region of uniform thickness and relatively thin with respect to said source and drain regions is formed; and (c) forming a Schottky-barrier gate electrode through evaporation of a metal primarily on said flat horizontal lower surface using said resist mask as an evaporation mask.

Claim 15

In a method for fabricating a gallium arsenide Schottky-barrier gate field effect transistor including the steps of forming a conducting channel on a surface of a semi-insulating gallium arsenide substrate, establishing source and drain ohmic contacts on predetermined portions of a surface of said conducting channel and thereby defining source and drain regions respectively, the improvement which comprises: (a) forming a resist etching mask on said conducting channel having an opening located between said source and drain contacts and closer to said source contact than to said drain contact; (b) forming a trapezoidal shaped inverted mesa cavity region in said conducting channel between said source and drain contacts and closer to said source contact than to said drain contact, by applying a preferential chemical etchant through said opening in said resist mask for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to the interface between said substrate and said conducting channel and angled said walls of said cavity region extending to said surface of said conducting channel at edges remote from said source and drain contacts, whereby a shallow conducting channel region of uniform thickness and relatively thin with respect to said source and drain regions is formed; and (c) forming a Schottky-barrier gate electrode through evaporation of a metal primarily on said flat horizontal lower surface using said resist mask as an evaporation mask.

Claim 16

A process for fabricating a self-aligned Schottky-barrier gate gallium arsenide transistor comprising the steps of: (a) forming a conducting channel on a surface of a semi-insulating gallium arsenide substrate and defining a substrate-conducting channel interface; (b) removing through etching an annular portion of said conducting channel providing an insulated mesa-like conducting channel portion on said substrate; (c) forming source and drain ohmic contacts on predetermined areas of a surface of said conducting channel portion, said areas defining a source region and a drain region respectively; (d) forming a photoresist etching mask on said channel portion having an opening of predetermined size and located between said source and drain contacts and relatively close to said source contact; (e) forming a trapezoidal shaped inverted mesa cavity region in said conducting channel, between said source and drain ohmic contacts, by applying a preferential chemical etchant through an opening in said photoresist mask for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to said substrate-conducting channel interface and angled side walls of said cavity region extending to said surface of said conducting channel at edges remote from said source and drain ohmic contacts, whereby there is formed a shallow conducting channel region of uniform thickness and relatively thin with respect to said source region and said drain region, whose size and location is determined by said photoresist mask; and (f) evaporating a predetermined metal in said opening in said photoresist mask, using said photoresist mask as an evaporation mask for the formation of a Schottky-barrier gate electrode primarily on said shallow conducting channel region; and (g) removing said photoresist mask to thereby leave said Schottky-barrier gate electrode formed on said shallow conducting channel region.

Claim 17

A process for fabricating a self-aligned Schottky-barrier gate gallium arsenide transistor comprising the steps of: (a) forming a conducting channel on a surface of a semi-insulating gallium arsenide substrate and defining a substrate-conducting channel interface; (b) removing through etching an annular portion of said conducting channel providing an insulated mesa-like conducting channel portion on said substrate; (c) forming source and drain ohmic contacts on predetermined areas of a surface of said conducting channel portion, said areas defining a source region and a drain region respectively; (d) forming a photoresist etching mask on said channel portion having an opening of predetermined size and located between said source and drain contacts and relatively close to said source contact; (e) forming a trapezoidal shaped inverted mesa cavity region in said conducting channel, between said source and drain ohmic contacts, by applying a preferential chemical etchant through an opening in said photoresist mask for a time sufficient to establish a flat horizontal lower surface of said cavity region parallel to said substrate-conducting channel interface and angled side walls of said cavity region extending to said surface of said conducting channel at edges remote from said source and drain ohmic contacts, whereby there is formed a shallow conducting channel region of uniform thickness and relatively thin with respect to said source region and said drain region, whose size and location is determined by said photoresist mask; and (f) evaporating a predetermined metal in said opening in said photoresist mask, using said photoresist mask as an evaporation mask for the formation of a Schottky-barrier gate electrode primarily on said shallow conducting channel region; and (g) removing said photoresist mask to thereby leave said Schottky-barrier gate electrode formed on said shallow conducting channel region.

Claim 18

A process for fabricating a field effect transistor structure comprising the steps of: (a) providing a substrate of semi-insulating gallium arsenide with a <100> crystallographic orientation; (b) forming a conducting channel on a surface of said substrate and defining a substrate-conducting channel interface; (c) establishing source and drain ohmic contacts on predetermined portions of a surface of said conducting channel, said portions defining a source region and a drain region respectively; (d) controllably and anisotropically etching a cavity in said conducting channel between said source and drain ohmic contacts, to a predetermined thickness above said substrate-conducting channel interface, said cavity having angled side walls and an adjoining bottom wall defining a trapezoidal shaped inverted mesa region and said angled side walls extending to said surface of said conducting channel at edges remote from said source and drain ohmic contacts, to thereby form a conducting channel region that is relatively thin with respect to said source region and said drain region; and (e) depositing a gate electrode member primarily on said bottom wall of said cavity and with minimal contact with said side walls thereof for minimizing parasitic coupling between said gate member and said conducting channel.

Claim 19

A process for fabricating a field effect transistor structure comprising the steps of: (a) providing a substrate of semi-insulating gallium arsenide with a <100> crystallographic orientation; (b) forming a conducting channel on a surface of said substrate and defining a substrate-conducting channel interface; (c) establishing source and drain ohmic contacts on predetermined portions of a surface of said conducting channel, said portions defining a source region and a drain region respectively; (d) controllably and anisotropically etching a cavity in said conducting channel between said source and drain ohmic contacts, to a predetermined thickness above said substrate-conducting channel interface, said cavity having angled side walls and an adjoining bottom wall defining a trapezoidal shaped inverted mesa region and said angled side walls extending to said surface of said conducting channel at edges remote from said source and drain ohmic contacts, to thereby form a conducting channel region that is relatively thin with respect to said source region and said drain region; and (e) depositing a gate electrode member primarily on said bottom wall of said cavity and with minimal contact with said side walls thereof for minimizing parasitic coupling between said gate member and said conducting channel.