Process for producing self aligned gate field effect transistor

Claim 1

A process for preparing a semiconductor device comprising: 1.growing a first epitaxial layer of a semiconductor material having a first-type of semiconductivity upon a substrate of the same semiconductive material but having a second-type of semiconductivity, 2. growing a second epitaxial layer of the semiconductor material over said first epitaxial layer, said second epitaxial layer being of the same type of semiconductivity as said first epitaxial layer but being more heavily doped than said first layer, 3. forming a layer of silicon nitride over said second epitaxial layer, 4. etching an aperture entirely through said layer of silicon nitride and said second epitaxial layer and into a portion of said first epitaxial layer, said aperture being of a greater cross-sectional area in said second epitaxial layer than in said silicon nitride layer , 5. forming a silicon oxide layer on the silicon nitride layer and over the side walls and bottom of the aperture, 6. depositing a gold layer over the silicon oxide layer disposed over the silicon nitride layer and on the bottom surface of the aperture, the pattern of the gold layer on the bottom surface of the aperture corresponding to a vertical projection of the aperture through the silicon nitride layer plus a small peripheral increment, 7. etching away that portion of the silicon oxide layer not covered by the gold layer, 8. etching away the gold layer thereby exposing the silicon oxide layer, 9. diffusing a dopant capable of imparting said first-type of semiconductivity into that portion of the side walls of the aperture not covered by the oxide layer, 10. removing the remaining silicon oxide layer, 11. etching contact apertures for electrical contacts through the nitride layer, said apertures extending to the second epitaxial layer, 12. depositing metal electrical contacts onto said second epitaxial layer through said contact apertures, and 13. depositing a metal electrical gate contact onto the bottom surface of said aperture, said metal electrical gate contact being a vertical projection of the aperture through said silicon nitride layer.