Ion Implanted gallium arsenide semiconductor devices fabricated in semi-insulating gallium arsenide substrates

Claim 2

A GAAS WAFER COMPRISING A GAAS SEMI-INSULATING SUBSTRATE WITH A BULK RESISTIVITY BETWEEN 10**6 AND 10**8 OHM CENTIMETERS AND HAVING A THIN ION IMPLANTED SURFACE REGION THEREIN, SAID REGION FORMED IN A SURFACE PAORTION OF SAID SUBSTRATE AND HAVING A UNIFORM THICKNESS OF ABOUT 0.2 MICROMETERS OR LESS OVER A PREDETERMINED AREA OF SAID SUBSTRATE, SAID ION IMPLANTED REGION CHARACTERIZED BY AN IMPURITY CONCINTRATION OF AT LEAST 10**17 CARRIERS PER CUBIC CENTIMETER BEGINNING AT OR CLOSELY ADJACENT THE SURFACE OF SAID ION IMPLANTED REGION AND EXTENDING OVER AT LEAST ONE HALF OF ITS SAID THICKNESS, AND SAID ION IMPLANTED REGION FURHER CHARACTERIZED BY CARRIER MOBILITIES THEREIN IN EXCESS IF 3000 CM2/VOLT-SECOND.

Claim 3

An ion implanted electrically isolated resistor comprising: a. GaAs semi-insulating substrate having a bulk resistivity between 106-108 ohm centimeters, b. a thin ion implanted surface region formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carriers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second; and c. spaced-apart metal contacts on said ion implanted region for making ohmic connection to said resistor.

Claim 4

An ion implanted electrically isolated resistor comprising: a. GaAs semi-insulating substrate having a bulk resistivity between 106-108 ohm centimeters, b. a thin ion implanted surface region formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carriers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second; and c. spaced-apart metal contacts on said ion implanted region for making ohmic connection to said resistor.

Claim 5

An electrically isolated double implanted diode comprising: a. a GaAs substrate having a bulk resistivity in the range of 106-108 ohm centimeters, b. an N-type ion implanted region, formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carriers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second, c. a P-type ion implanted region bounded by said N-type region and defining therewith a PN junction, d. a surface passivating coating covering said PN junction and having openings therein, and e. metal contacts in said openings for applying bias to said PN junction.

Claim 6

An electrically isolated double implanted diode comprising: a. a GaAs substrate having a bulk resistivity in the range of 106-108 ohm centimeters, b. an N-type ion implanted region, formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carriers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second, c. a P-type ion implanted region bounded by said N-type region and defining therewith a PN junction, d. a surface passivating coating covering said PN junction and having openings therein, and e. metal contacts in said openings for applying bias to said PN junction.

Claim 7

An electrically isolated Schottky-barrier diode comprising: a. a GAAs semi-insulating substrate having a bulk resistivity in the range of 106-108 ohm centimeters and being doped with chromium in excess of 0.01 parts per million, b. said GaAs substrates including therein an N-type ion implanted and electrically activated region formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carriers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second, c. a Schottky-barrier contact bonded at one selected area of said implanted region and forming therewith a Schottky-barrier junction, and d. an ohmic contact bonded to another selected area of said implanted region.

Claim 8

An electrically isolated Schottky-barrier diode comprising: a. a GAAs semi-insulating substrate having a bulk resistivity in the range of 106-108 ohm centimeters and being doped with chromium in excess of 0.01 parts per million, b. said GaAs substrates including therein an N-type ion implanted and electrically activated region formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carriers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second, c. a Schottky-barrier contact bonded at one selected area of said implanted region and forming therewith a Schottky-barrier junction, and d. an ohmic contact bonded to another selected area of said implanted region.

Claim 9

The diode in claim 4 wherein said N-type region is sulfur ion implanted at an ion dosage of between 1011/cm2 and 1014/cm2.

Claim 10

A Schottky-barrier-gate field effect transistor comprising: a. a semi-insulating GaAs substrate having a resistivity in the range of 106-108 ohm centimeters, b. an ion implanted N-channel region selectively formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carrIers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second, c. spaced-apart ohmic contacts formed on the surface of said ion implanted N-channel region to thereby form source and drain electrodes for said Schottky-barrier-gate field effect transistor, and d. a thin strip of metallization located between said source and drain electrodes and in intimate contact with said ion implanted region, whereby gate voltages applied to said gate electrode are operative to control the conductivity in said ion implanted N-channel region between said source and drain electrodes of said transistor, and the capacitive coupling from said channel region through said substrate is minimized.

Claim 11

A Schottky-barrier-gate field effect transistor comprising: a. a semi-insulating GaAs substrate having a resistivity in the range of 106-108 ohm centimeters, b. an ion implanted N-channel region selectively formed in a surface portion of said substrate and having a uniform thickness of about 0.2 micrometers or less over a predetermined area of said substrate, said ion implanted region characterized by an impurity concentration of at least 1017 carrIers per cubic centimeter beginning at or closely adjacent the surface of said ion implanted region and extending over at least one half of its said thickness, and said region further characterized by carrier mobilities therein in excess of 3000 cm2/volt.second, c. spaced-apart ohmic contacts formed on the surface of said ion implanted N-channel region to thereby form source and drain electrodes for said Schottky-barrier-gate field effect transistor, and d. a thin strip of metallization located between said source and drain electrodes and in intimate contact with said ion implanted region, whereby gate voltages applied to said gate electrode are operative to control the conductivity in said ion implanted N-channel region between said source and drain electrodes of said transistor, and the capacitive coupling from said channel region through said substrate is minimized.

Claim 12

The device defined in claim 6 wherein said N-channel region is sulfur ion, S , implanted with a relatively uniform carrier concentration over a thickness of between 0.1-0.2 micrometers.

Claim 13

The device defined in claim 6 wherein said N-channel region has a mesa configuration and is integral with said semi-insulating substrating which serves to electrically isolate said transistor from other components or devices on or in said substrate.