US4077111A
Expired / Lapsed
US
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Self-aligned gate field effect transistor and method for making same
Assignee: Westinghouse Electric Corp
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Filing: 1976-07-14
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Granted: 1978-03-07
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Expires: 1996-07-14
Abstract
Abstract A self-aligned gate field effect transistor is described which is capable of operating at high frequencies. A method for making the transistor is described which comprises plating metal partially over an oxide layer, then removing the oxide to produce an overlapping metal portion and then plating again to produce a gate contact between the overlapping metal portions.
Inventors
- 👤 Michael C. Driver
- 👤 He B. Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:02
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/80; H10D30/87; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/646; Y; Y10; Y10S; Y10S148/00; Y10S148/143
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
133 words
A method of making a self-aligned gate field effect transistor comprising the steps: a. forming an N-type GaAs channel region on a semi-insulating GaAs substrate, b. forming a layer of SiO 2 masking a portion of the channel region, c. etching through unmasked portions of the channel region to expose portions of the substrate, d. epitaxially growing N + -type source and drain regions on the exposed portions of the substrate, e. depositing source and drain electrodes on the source and drain regions and partially overlapping the SiO 2 layer, f. removing the SiO 2 layer, and g. depositing a gate electrode on the channel region while using said partially overlapping portions of the source and drain electrodes as masks to space the gate electrodes from each of the source and drain electrodes.
Claim 2
Independent Claim
133 words
A method of making a self-aligned gate field effect transistor comprising the steps: a. forming an N-type GaAs channel region on a semi-insulating GaAs substrate, b. forming a layer of SiO 2 masking a portion of the channel region, c. etching through unmasked portions of the channel region to expose portions of the substrate, d. epitaxially growing N + -type source and drain regions on the exposed portions of the substrate, e. depositing source and drain electrodes on the source and drain regions and partially overlapping the SiO 2 layer, f. removing the SiO 2 layer, and g. depositing a gate electrode on the channel region while using said partially overlapping portions of the source and drain electrodes as masks to space the gate electrodes from each of the source and drain electrodes.
Claim 3
Dependent Claim
18 words
The method of claim 1 wherein in step (b) the SiO 2 layer is about one micron thick.
Claim 4
Dependent Claim
29 words
The method of claim 1 wherein in step (c) the channel region is etched with H 2 SO 4 :H 2 O:H 2 O 2 in the ration 50:1:2.
Claim 5
Dependent Claim
23 words
The method of claim 1 wherein in step (d) the source and drain regions are additionally grown on edges of the channel region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-06 | 1981-09-05 | 1982-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-06 | 1985-09-05 | 1986-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-06 | 1989-09-05 | 1990-03-07 | $7700.00 | Window Closed / Lapsed |