Method of forming trench transistor with source contact in trench

Claim 1

A method of forming an IGFET, comprising the steps of: forming a trench in a substrate, wherein the trench includes first and second opposing sidewalls and a bottom surface; forming a gate insulator on the bottom surface; forming a gate electrode on the gate insulator; forming a first insulative spacer adjacent to the first sidewall, a second insulative spacer adjacent to the gate electrode and the second sidewall, and a third insulative spacer adjacent to the gate electrode, wherein a contact portion of the bottom surface between the first and third insulative spacers is exposed; forming a source and a drain in the substrate and adjacent to the bottom surface; and forming a source contact and a drain contact, wherein the source contact is in the trench and electrically coupled to the source at the contact portion of the bottom surface, and the drain contact is electrically coupled to the drain at a top surface of the substrate.

Claim 2

A method of forming an IGFET, comprising the steps of: forming a trench in a substrate, wherein the trench includes first and second opposing sidewalls and a bottom surface; forming a gate insulator on the bottom surface; forming a gate electrode on the gate insulator; forming a first insulative spacer adjacent to the first sidewall, a second insulative spacer adjacent to the gate electrode and the second sidewall, and a third insulative spacer adjacent to the gate electrode, wherein a contact portion of the bottom surface between the first and third insulative spacers is exposed; forming a source and a drain in the substrate and adjacent to the bottom surface; and forming a source contact and a drain contact, wherein the source contact is in the trench and electrically coupled to the source at the contact portion of the bottom surface, and the drain contact is electrically coupled to the drain at a top surface of the substrate.

Claim 29

A method of forming an IGFET in a trench, comprising the steps of: providing a semiconductor substrate; implanting a doped layer into the substrate; then forming a first photoresist layer with an opening over the substrate; applying an anisotropic etch through the opening in the first photoresist layer to form a trench completely through the doped layer and partially through the substrate, wherein the trench has first and second opposing sidewalls and a bottom surface, and the trench splits the doped layer into sidewall source and drain regions, with the sidewall source region adjacent to the first sidewall and spaced from the bottom surface, and the sidewall drain region adjacent to the second sidewall and spaced from the bottom surface; stripping the first photoresist layer; then forming disposable spacers on the sidewalls and on outer portions of the bottom surface adjacent to the sidewalls while exposing a central portion of the bottom surface between the outer portions; growing an oxide layer on the central portion of the bottom surface; depositing a polysilicon layer over the substrate and on the disposable spacers and the oxide layer; polishing the polysilicon layer until the polysilicon layer is planarized and does not overlap the first and second sidewalls; then removing at least portions of the disposable spacers to form voids in the trench between the polysilicon layer and the sidewalls; implanting a localized drain region through one of the voids and the bottom surface into the substrate using the polysilicon layer as an implant mask for the central portion of the bottom surface; then forming a second photoresist layer over the substrate, wherein the second photoresist layer includes an opening above a first lateral portion of the trench that includes the first sidewall, and the second photoresist layer covers a second lateral portion of the trench that includes the localized drain region and the second sidewall; applying an anisotropic etch through the opening in the second photoresist layer to remove the polysilicon layer in the first lateral portion of the trench, thereby forming a polysilicon gate electrode in the second lateral portion of the trench, wherein the polysilicon gate electrode is spaced from and electrically isolated from the substrate, and the polysilicon gate electrode is substantially closer to the second sidewall than to the first sidewall; then removing the oxide layer in the first lateral portion of the trench, thereby forming a gate oxide beneath the polysilicon gate electrode in the second lateral portion of the trench; implanting a localized source region through the first lateral portion of the trench and the bottom surface into the substrate, wherein the localized source region is outside the second lateral portion of the trench; stripping the second photoresist layer; forming first, second and third insulative spacers in the trench, wherein the first insulative spacer is adjacent to the first sidewall, the second insulative spacer is adjacent to the polysilicon gate electrode and the second sidewall, the third insulative spacer is adjacent to the polysilicon gate electrode on a side opposite the second insulative spacer, and a contact portion of the bottom surface between the first and third insulative spacers is exposed; then applying a high-temperature anneal to form a source and a drain in the substrate, wherein the source includes the localized source region merged with the sidewall source region, the drain includes the localized drain region merged with the sidewall drain region, and the localized source and drain regions define a channel in the substrate adjacent to the bottom surface; forming an insulative layer with contact windows over the substrate; and forming metallic source and drain contacts that extend through the contact windows, wherein the source contact is substantially closer to the first sidewall than to the second sidewall and includes first and second silicide regions that are electrically coupled to the source at the contact portion of the bottom surface and the top surface, respectively, and the drain contact is substantially closer to the second sidewall than to the first sidewall and is spaced from the bottom surface and includes a single silicide region that is electrically coupled to the sidewall drain region at the top surface.

Claim 30

A method of forming an IGFET in a trench, comprising the steps of: providing a semiconductor substrate; implanting a doped layer into the substrate; then forming a first photoresist layer with an opening over the substrate; applying an anisotropic etch through the opening in the first photoresist layer to form a trench completely through the doped layer and partially through the substrate, wherein the trench has first and second opposing sidewalls and a bottom surface, and the trench splits the doped layer into sidewall source and drain regions, with the sidewall source region adjacent to the first sidewall and spaced from the bottom surface, and the sidewall drain region adjacent to the second sidewall and spaced from the bottom surface; stripping the first photoresist layer; then forming disposable spacers on the sidewalls and on outer portions of the bottom surface adjacent to the sidewalls while exposing a central portion of the bottom surface between the outer portions; growing an oxide layer on the central portion of the bottom surface; depositing a polysilicon layer over the substrate and on the disposable spacers and the oxide layer; polishing the polysilicon layer until the polysilicon layer is planarized and does not overlap the first and second sidewalls; then removing at least portions of the disposable spacers to form voids in the trench between the polysilicon layer and the sidewalls; implanting a localized drain region through one of the voids and the bottom surface into the substrate using the polysilicon layer as an implant mask for the central portion of the bottom surface; then forming a second photoresist layer over the substrate, wherein the second photoresist layer includes an opening above a first lateral portion of the trench that includes the first sidewall, and the second photoresist layer covers a second lateral portion of the trench that includes the localized drain region and the second sidewall; applying an anisotropic etch through the opening in the second photoresist layer to remove the polysilicon layer in the first lateral portion of the trench, thereby forming a polysilicon gate electrode in the second lateral portion of the trench, wherein the polysilicon gate electrode is spaced from and electrically isolated from the substrate, and the polysilicon gate electrode is substantially closer to the second sidewall than to the first sidewall; then removing the oxide layer in the first lateral portion of the trench, thereby forming a gate oxide beneath the polysilicon gate electrode in the second lateral portion of the trench; implanting a localized source region through the first lateral portion of the trench and the bottom surface into the substrate, wherein the localized source region is outside the second lateral portion of the trench; stripping the second photoresist layer; forming first, second and third insulative spacers in the trench, wherein the first insulative spacer is adjacent to the first sidewall, the second insulative spacer is adjacent to the polysilicon gate electrode and the second sidewall, the third insulative spacer is adjacent to the polysilicon gate electrode on a side opposite the second insulative spacer, and a contact portion of the bottom surface between the first and third insulative spacers is exposed; then applying a high-temperature anneal to form a source and a drain in the substrate, wherein the source includes the localized source region merged with the sidewall source region, the drain includes the localized drain region merged with the sidewall drain region, and the localized source and drain regions define a channel in the substrate adjacent to the bottom surface; forming an insulative layer with contact windows over the substrate; and forming metallic source and drain contacts that extend through the contact windows, wherein the source contact is substantially closer to the first sidewall than to the second sidewall and includes first and second silicide regions that are electrically coupled to the source at the contact portion of the bottom surface and the top surface, respectively, and the drain contact is substantially closer to the second sidewall than to the first sidewall and is spaced from the bottom surface and includes a single silicide region that is electrically coupled to the sidewall drain region at the top surface.