US5610091A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a non-volatile memory cell
Assignee: SK Hynix Inc
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Filing: 1995-09-08
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Granted: 1997-03-11
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Expires: 2015-09-08
Abstract
Abstract A method for manufacturing a non-volatile memory cell which can improve the reliability and electrical operation characteristics of a memory cell by making a recess structure of a silicon substrate of a channel region in order to increase capacitance coupling ratio between a control gate and a floating gate is disclosed.
Inventors
- 👤 Byung J. Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:19
CPC Classifications
H; H10; H10B; H10B41/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
185 words
A method for manufacturing a non-volatile memory cell, comprising the steps of: sequentially forming a pad oxide layer and a nitride layer on a silicon substrate having a field oxide layer; patterning said nitride layer so as to expose a selected portion of said pad oxide layer; forming a cell oxidation layer by oxidizing the selection portion of said pad oxide layer; etching an exposed portion of said cell oxidation layer by an etching process using said patterned nitride layer as an etch barrier, thereby forming a recess in said silicon substrate and leaving an unexposed portion of said cell oxidation layer; forming a tunnel oxide layer on said silicon substrate exposed by etching said cell oxidation layer; sequentially forming a first conductive layer, a dielectric layer and a second conductive layer on the resulting structure after forming said tunnel oxide layer; forming a stacked gate electrode at the recess by sequentially patterning said second conductive layer, said dielectric layer and said first conductive layer, and forming source and drain regions by injecting an impurity into said silicon substrate and then annealing said silicon substrate.
Claim 2
Independent Claim
185 words
A method for manufacturing a non-volatile memory cell, comprising the steps of: sequentially forming a pad oxide layer and a nitride layer on a silicon substrate having a field oxide layer; patterning said nitride layer so as to expose a selected portion of said pad oxide layer; forming a cell oxidation layer by oxidizing the selection portion of said pad oxide layer; etching an exposed portion of said cell oxidation layer by an etching process using said patterned nitride layer as an etch barrier, thereby forming a recess in said silicon substrate and leaving an unexposed portion of said cell oxidation layer; forming a tunnel oxide layer on said silicon substrate exposed by etching said cell oxidation layer; sequentially forming a first conductive layer, a dielectric layer and a second conductive layer on the resulting structure after forming said tunnel oxide layer; forming a stacked gate electrode at the recess by sequentially patterning said second conductive layer, said dielectric layer and said first conductive layer, and forming source and drain regions by injecting an impurity into said silicon substrate and then annealing said silicon substrate.
Claim 3
Dependent Claim
42 words
The method of claim 1, wherein said cell oxidation layer is, first etched by a dry etching process until the thickness of said cell oxidation layer is 200 to 300 Å and the residual is then etched by a wet etching process.
Claim 4
Dependent Claim
17 words
The method of claim 1, wherein said cell oxidation layer is etched by a dry etching process.
References Cited (Backward Citations)
JPH04111470A
Cited
US5376572A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |