Method of making an electrically erasable programmable memory device with improved erase and write operation

Claim 1

A method of forming an improved electrically erasable programmable read only memory device having, adjacent to a source region, a doped tunneling region which fully underlies a floating gate region and a surface depression over said doped region comprising the steps of: providing a semiconductor substrate having a background dopant of a first conductivity type; forming a thin insulating layer on a surface of the semiconductor substrate; forming an oxidation resistant masking layer over the thin insulating layer; forming first openings in the oxidation resistant masking layer that define a thick field oxide layer and a second opening which defines the doped tunneling region; growing said thick field oxide layer in said first openings and forming a thick oxide in said second opening so that said thick oxide is exposed; removing the oxidation masking layer; forming a resist layer over the substrate surface with a third opening over said second opening; removing the exposed thick oxide in said third openings thereby forming a depression in the substrate surface and partially exposing said substrate surface; implanting ions of a second conductivity type into the substrate through the third opening thereby forming said doped tunneling region; removing the resist layer; removing the thin insulation layer to expose the substrate; forming a tunnel oxide layer on the exposed substrate which at least fully overlies the tunneling region; forming a floating gate on the tunnel oxide layer that at least fully overlaps said doped tunneling region; forming a gate insulation layer on the floating gate layer; forming a control gate layer over the floating gate layer; forming an ion implantation masking layer with fourth openings which define source and drain regions; implanting ions of a second conductivity type through the fourth openings into said substrate to form source and drain regions; forming a dielectric layer over the control gate electrode and said substrate; and forming electrical contacts and metallurgical interconnect lines, and electrically connecting the source, drain, and floating and control gates to form an electrically programmable memory device.

Claim 2

A method of forming an improved electrically erasable programmable read only memory device having, adjacent to a source region, a doped tunneling region which fully underlies a floating gate region and a surface depression over said doped region comprising the steps of: providing a semiconductor substrate having a background dopant of a first conductivity type; forming a thin insulating layer on a surface of the semiconductor substrate; forming an oxidation resistant masking layer over the thin insulating layer; forming first openings in the oxidation resistant masking layer that define a thick field oxide layer and a second opening which defines the doped tunneling region; growing said thick field oxide layer in said first openings and forming a thick oxide in said second opening so that said thick oxide is exposed; removing the oxidation masking layer; forming a resist layer over the substrate surface with a third opening over said second opening; removing the exposed thick oxide in said third openings thereby forming a depression in the substrate surface and partially exposing said substrate surface; implanting ions of a second conductivity type into the substrate through the third opening thereby forming said doped tunneling region; removing the resist layer; removing the thin insulation layer to expose the substrate; forming a tunnel oxide layer on the exposed substrate which at least fully overlies the tunneling region; forming a floating gate on the tunnel oxide layer that at least fully overlaps said doped tunneling region; forming a gate insulation layer on the floating gate layer; forming a control gate layer over the floating gate layer; forming an ion implantation masking layer with fourth openings which define source and drain regions; implanting ions of a second conductivity type through the fourth openings into said substrate to form source and drain regions; forming a dielectric layer over the control gate electrode and said substrate; and forming electrical contacts and metallurgical interconnect lines, and electrically connecting the source, drain, and floating and control gates to form an electrically programmable memory device.

Claim 3

A method of forming an improved electrically erasable programmable read only memory device comprising the steps of: providing a semiconductor substrate having a surface and having a background dopant of a first conductivity type; forming an oxide region on the substrate; removing the oxide thereby forming a depression in the substrate surface; forming a doped tunneling region in the substrate surface below said depression; forming a tunnel oxide layer on the substrate surface that fully overlies said doped tunneling region; forming a floating gate on the tunnel oxide layer; forming a gate insulation layer on the floating gate layer; forming a control gate over the floating gate layer; forming spaced source and drain regions in the substrate separated by a channel region, with the source adjacent to the doped tunneling region, with said doped tunneling region adjacent to the channel region, and the channel region adjacent to the drain; forming a dielectric layer over the control gate electrode and substrate; forming electrical contacts and metallurgical interconnection lines; and electrically connecting the source, drain, and floating and control gates to form an electrically programmable memory device.

Claim 4

A method of forming an improved electrically erasable programmable read only memory device comprising the steps of: providing a semiconductor substrate having a surface and having a background dopant of a first conductivity type; forming an oxide region on the substrate; removing the oxide thereby forming a depression in the substrate surface; forming a doped tunneling region in the substrate surface below said depression; forming a tunnel oxide layer on the substrate surface that fully overlies said doped tunneling region; forming a floating gate on the tunnel oxide layer; forming a gate insulation layer on the floating gate layer; forming a control gate over the floating gate layer; forming spaced source and drain regions in the substrate separated by a channel region, with the source adjacent to the doped tunneling region, with said doped tunneling region adjacent to the channel region, and the channel region adjacent to the drain; forming a dielectric layer over the control gate electrode and substrate; forming electrical contacts and metallurgical interconnection lines; and electrically connecting the source, drain, and floating and control gates to form an electrically programmable memory device.