US5318921A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making a high density ROM or EPROM integrated circuit
Assignee: United Microelectronics Corp
•
Filing: 1993-05-03
•
Granted: 1994-06-07
•
Expires: 2013-05-03
Abstract
Abstract An insulating layer structure is formed over semiconductor device structures in and on a semiconductor substrate. A conductive polysilicon layer covers the insulating layer which is covered by a silicon oxide layer. The oxide layer is now patterned by lithography and etching. This patterning leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines. A uniform thickness silicon nitride layer is deposited over the oxide layer and the exposed polysilicon layer wherein the thickness is the width of the planned spacing. The nitride layer is anisotropically etched to produce sidewall structures having the width of the planned spacing. The exposed polysilicon layer is oxidized. The sidewall structures are removed by etching. The exposed polysilicon layer is anisotropically etched to form closely spaced polysilicon conductor lines. The silicon oxide layers over the polysilicon conductor lines are removed as by etching. N+ ions are implanted into the silicon substrate under the spacing between the polysilicon conductor lines to form bit lines. An insulating layer structure is formed over the bit lines. Processing continues as before to form a second set of polysilicon lines which form the word lines.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Ming-Tzong Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:45
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10W; H10W20/00; H10W20/01
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
491 words
The method of manufacturing closely spaced, parallel, single level polysilicon conductor lines which are perpendicular to buried N+ regions in a silicon substrate in a ROM integrated circuit comprising: forming semiconductor device structures in and on a semiconductor substrate; forming a first insulating layer structure over said semiconductor device structures; forming a first conductive polysilicon layer over said first insulating layer; forming a first silicon oxide layer over said first polysilicon layer and patterning said first oxide layer; said patterning of said first oxide layer leaves a first pattern of said first oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said first oxide which exposes said first polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness first silicon nitride layer over said first oxide layer and said first exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said first nitride layer to produce first sidewall structures having the width of said planned spacing and leaving exposed portions of said first polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said first polysilicon layer; removing said first sidewall structures by etching; anisotropically etching the exposed said first polysilicon layer to form first said closely spaced polysilicon conductor lines; removing said first oxide layers over said first polysilicon conductor lines; implanting N+ ions into said silicon substrate under the spacing between said first polysilicon conductor lines to form said buried N+ regions; removing said first exposed polysilicon layer and said first insulating layer; forming a second insulating layer structure over said first closely spaced polysilicon conductor lines; forming a second conductor polysilicon layer over said second insulating layer; forming a second silicon oxide layer over said second polysilicon layer and patterning said second oxide layer; said patterning of said second oxide layer leaves a first pattern of said second oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said second oxide which expose said second polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness second silicon nitride layer over said second oxide layer and said second exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said second nitride layer to produce second sidewall structures having the width of said planned spacing and leaving exposed portions of said second polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said second polysilicon layer; removing said second sidewall structures by etching; anisotropically etching the exposed said second polysilicon layer to form second said closely spaced polysilicon conductor lines; and electrically connecting said first and second polysilicon lines to form said ROM integrated circuit.
Claim 2
Independent Claim
491 words
The method of manufacturing closely spaced, parallel, single level polysilicon conductor lines which are perpendicular to buried N+ regions in a silicon substrate in a ROM integrated circuit comprising: forming semiconductor device structures in and on a semiconductor substrate; forming a first insulating layer structure over said semiconductor device structures; forming a first conductive polysilicon layer over said first insulating layer; forming a first silicon oxide layer over said first polysilicon layer and patterning said first oxide layer; said patterning of said first oxide layer leaves a first pattern of said first oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said first oxide which exposes said first polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness first silicon nitride layer over said first oxide layer and said first exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said first nitride layer to produce first sidewall structures having the width of said planned spacing and leaving exposed portions of said first polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said first polysilicon layer; removing said first sidewall structures by etching; anisotropically etching the exposed said first polysilicon layer to form first said closely spaced polysilicon conductor lines; removing said first oxide layers over said first polysilicon conductor lines; implanting N+ ions into said silicon substrate under the spacing between said first polysilicon conductor lines to form said buried N+ regions; removing said first exposed polysilicon layer and said first insulating layer; forming a second insulating layer structure over said first closely spaced polysilicon conductor lines; forming a second conductor polysilicon layer over said second insulating layer; forming a second silicon oxide layer over said second polysilicon layer and patterning said second oxide layer; said patterning of said second oxide layer leaves a first pattern of said second oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said second oxide which expose said second polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness second silicon nitride layer over said second oxide layer and said second exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said second nitride layer to produce second sidewall structures having the width of said planned spacing and leaving exposed portions of said second polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said second polysilicon layer; removing said second sidewall structures by etching; anisotropically etching the exposed said second polysilicon layer to form second said closely spaced polysilicon conductor lines; and electrically connecting said first and second polysilicon lines to form said ROM integrated circuit.
Claim 3
Dependent Claim
26 words
The method of claim 1 wherein said buried N+ regions are connected as bit lines and said second polysilicon conductor lines are connected as word lines.
Claim 4
Dependent Claim
32 words
The method of claim 1 wherein said first and second polysilicon layers have a thickness of between about 1000 to 6000 Angstroms and are doped with phosphorus after deposition using phosphorus oxychloride.
Claim 5
Dependent Claim
25 words
The method of claim 1 wherein said first and second silicon oxide layers are formed to a thickness of between about 1000 to 6000 Angstroms.
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein said first and second silicon nitride layers have a thickness of between about 500 to 5000 Angstroms.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein said anisotropic etching ambient for etching said polysilicon layers is composed of chlorine/helium.
Claim 8
Dependent Claim
19 words
The method of claim 1 wherein said etching of said silicon nitride sidewall layers is done using phosphoric acid.
Claim 9
Dependent Claim
55 words
The method of claim 1 wherein said first closely spaced polysilicon lines are used as closely spaced polysilicon bit lines, said second closely spaced polysilicon lines are used as closely spaced polysilicon word lines, and floating gate and gate dielectric structures are provided, and said lines and structures are connected as an EPROM integrated circuit.
Claim 10
Independent Claim
503 words
The method of manufacturing closely spaced, parallel, single level polysilicon conductor lines which are perpendicular to buried N+ regions in a silicon substrate in a EPROM integrated circuit comprising: forming semiconductor device structures in and on a semiconductor substrate; forming a first insulating layer structure over said semiconductor device structures; forming a first conductive polysilicon layer over said first insulating layer; forming a first silicon oxide layer over said first polysilicon layer and patterning said first oxide layer; said patterning of said first oxide layer leaves a first pattern of said first oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said first oxide which exposes said first polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness first silicon nitride layer over said first oxide layer and said first exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said first nitride layer to produce first sidewall structures having the width of said planned spacing and leaving exposed portions of said first polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said first polysilicon layer; removing said first sidewall structures by etching; anisotropically etching the exposed said first polysilicon layer to form first said closely spaced polysilicon conductor lines; removing said first oxide layers over said first polysilicon conductor lines; implanting N+ ions into said silicon substrate under the spacing between said first polysilicon conductor lines to form said buried N+ regions; removing said first exposed polysilicon layer and said first insulating layer; forming a second insulating layer structure over said first closely spaced polysilicon conductor lines; forming a second conductor polysilicon layer over said second insulating layer; forming a second silicon oxide layer over said second polysilicon layer and patterning said second oxide layer; said patterning of said second oxide layer leaves a first pattern of said second oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said second oxide which expose said second polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness second silicon nitride layer over said second oxide layer and said second exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said second nitride layer to produce second sidewall structures having the width of said planned spacing and leaving exposed portions of said second polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said second polysilicon layer; removing said second sidewall structures by etching; anisotropically etching the exposed said second polysilicon layer to form second said closely spaced polysilicon conductor lines; and electrically connecting said first polysilicon lines as bit lines, floating gate structures and said second polysilicon lines as word lines to form said EPROM integrated circuit.
Claim 11
Independent Claim
503 words
The method of manufacturing closely spaced, parallel, single level polysilicon conductor lines which are perpendicular to buried N+ regions in a silicon substrate in a EPROM integrated circuit comprising: forming semiconductor device structures in and on a semiconductor substrate; forming a first insulating layer structure over said semiconductor device structures; forming a first conductive polysilicon layer over said first insulating layer; forming a first silicon oxide layer over said first polysilicon layer and patterning said first oxide layer; said patterning of said first oxide layer leaves a first pattern of said first oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said first oxide which exposes said first polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness first silicon nitride layer over said first oxide layer and said first exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said first nitride layer to produce first sidewall structures having the width of said planned spacing and leaving exposed portions of said first polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said first polysilicon layer; removing said first sidewall structures by etching; anisotropically etching the exposed said first polysilicon layer to form first said closely spaced polysilicon conductor lines; removing said first oxide layers over said first polysilicon conductor lines; implanting N+ ions into said silicon substrate under the spacing between said first polysilicon conductor lines to form said buried N+ regions; removing said first exposed polysilicon layer and said first insulating layer; forming a second insulating layer structure over said first closely spaced polysilicon conductor lines; forming a second conductor polysilicon layer over said second insulating layer; forming a second silicon oxide layer over said second polysilicon layer and patterning said second oxide layer; said patterning of said second oxide layer leaves a first pattern of said second oxide over a first designated plurality of polysilicon conductor lines and a second pattern between said second oxide which expose said second polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between said first and second plurality of polysilicon conductor lines; depositing a uniform thickness second silicon nitride layer over said second oxide layer and said second exposed polysilicon layer wherein said thickness is the width of said planned spacing; anisotropically etching said second nitride layer to produce second sidewall structures having the width of said planned spacing and leaving exposed portions of said second polysilicon layer of said second designated plurality of polysilicon lines; oxidizing the exposed said second polysilicon layer; removing said second sidewall structures by etching; anisotropically etching the exposed said second polysilicon layer to form second said closely spaced polysilicon conductor lines; and electrically connecting said first polysilicon lines as bit lines, floating gate structures and said second polysilicon lines as word lines to form said EPROM integrated circuit.
Claim 12
Dependent Claim
32 words
The method of claim 9 wherein said first and second polysilicon layers have a thickness of between about 1000 to 6000 Angstroms and are doped with phosphorus after deposition using phosphorus oxychloride.
Claim 13
Dependent Claim
22 words
The method of claim 9 wherein said silicon oxide layers are formed to a thickness of between about 1000 to 6000 Angstroms.
Claim 14
Dependent Claim
20 words
The method of claim 9 wherein said silicon nitride layers have a thickness of between about 500 to 5000 Angstroms.
Claim 15
Dependent Claim
20 words
The method of claim 9 wherein the said polysilicon lines are spaced less than about 0.8 micrometers from one another.
Claim 16
Dependent Claim
19 words
The method of claim 13 wherein said polysilicon lines are spaced less than about 0.3 micrometers from one another.
Claim 17
Dependent Claim
17 words
The method of claim 9 wherein said etching of said sidewall structures is by hot phosphoric acid.
References Cited (Backward Citations)
US4833514A
Cited
US5200355A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |