US4830975A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacture a primos device
Assignee: National Semiconductor Corp
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Filing: 1987-11-27
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Granted: 1989-05-16
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Expires: 2007-11-27
Abstract
Abstract A PRIMOS (Planar Recessed Isolated MOS) transistor and a method for fabricating same is described wherein the source and drain in a semiconductor body are separated by a recess. A gate oxide is disposed on the body in the recess, with conductive gate material thereon. Oxide regions are positioned on each side of the gate, such oxide regions being substantially thicker in cross-section than the gate oxide. The method described teaches fabrication of this device.
Inventors
- 👤 Arthur J. Bovaird
- 👤 Reza Fatemi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:46
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10D30/00; H10D30/60; H10D64/01; H10D64/025; H10D64/027; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; Y; Y10; Y10S; Y10S148/00; Y10S148/116; Y10S148/163; Y10S438/00; Y10S438/936
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
96 words
A method of fabricating a semiconductor device comprising: providing a body of a first conductivity type having first and second regions of a second conductivity type spaced apart by a recess in the body, the dopant level in the first and second regions varying adjacent the recess in the direction of the depth of the recess; and growing oxide material on portions of the first and second regions at a chosen temperature and pressure such that the rate of oxide growth is generally directly proportional to the level of concentration of dopant at such oxide growth.
Claim 2
Independent Claim
96 words
A method of fabricating a semiconductor device comprising: providing a body of a first conductivity type having first and second regions of a second conductivity type spaced apart by a recess in the body, the dopant level in the first and second regions varying adjacent the recess in the direction of the depth of the recess; and growing oxide material on portions of the first and second regions at a chosen temperature and pressure such that the rate of oxide growth is generally directly proportional to the level of concentration of dopant at such oxide growth.
Claim 3
Dependent Claim
22 words
The method of claim 1 wherein the dopant level adjacent the recess decreases in the direction of the depth of the recess.
Claim 4
Dependent Claim
37 words
The method of claim 2 and further comprising the step of providing an oxide layer of substantially uniform thickness in the recess, and providing polysilicon material in the recess prior to said step of growing oxide material.
Claim 5
Dependent Claim
26 words
The method of claim 2 and further comprising the step of providing a metal gate in the recess subsequent to the step of growing oxide material.
Claim 6
Independent Claim
138 words
A method of fabricating a semiconductor device comprising: providing a semiconductor body having a doped surface, an impurity concentration that decreases with depth into into said body and a recess therein, said recess being shaped to extend completely through said doped surface thereby to define a channel region in said semiconductor device; providing an oxide layer in said recess; providing a polysilicon layer on the oxide layer, said polysilicon layer being shaped to define a gate electrode on said oxide layer; providing a nitride layer on the polysilicon layer, said nitride layer being shaped to conform to said gate electode; and undertaking an oxidizing step so as to provide oxide portions of each side of the recess and exterior to the confines of said nitride layer which in cross-section taper inward in a direction inward of the recess.
Claim 7
Independent Claim
138 words
A method of fabricating a semiconductor device comprising: providing a semiconductor body having a doped surface, an impurity concentration that decreases with depth into into said body and a recess therein, said recess being shaped to extend completely through said doped surface thereby to define a channel region in said semiconductor device; providing an oxide layer in said recess; providing a polysilicon layer on the oxide layer, said polysilicon layer being shaped to define a gate electrode on said oxide layer; providing a nitride layer on the polysilicon layer, said nitride layer being shaped to conform to said gate electode; and undertaking an oxidizing step so as to provide oxide portions of each side of the recess and exterior to the confines of said nitride layer which in cross-section taper inward in a direction inward of the recess.
Claim 8
Dependent Claim
43 words
The method of claim 4 and further comprising the steps of providing an oxide layer in the recess and in contact with the semiconductor body and connecting the tapered oxide portions, and providing a polysilicon gate in the recess on such oxide layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |