Method of fabricating electrically eraseable read only memory cell having a trench

Claim 1

A methods of fabricating an electrically programmable read only memory cell on a semiconductor substrate comprising: forming an elongated trench in said substrate, forming a first insulating layer over the surface of said substrate, including the sidewalls and bottom of said trench, forming individual multiple pairs of spaced polycrystalline silicon layers on the opposed sidewalls of the trench, which form floating gates, implanting a first type dopant into said substrate thereby forming a continuous doped region in the bottom of said trench, which form a continuous source region, and also individual doped regions on opposite sides of the trench, adjacent to the top surface of the substrate, which form the drain regions, forming a second insulating layer over the said individual pairs of spaced polycrystalline silicon layers, forming a conductive control gate word line stripe over, and transverse to the trench adjacent to the individual polycrystalline silicon layers, and forming an electrical contact to the continuous doped region in the bottom of the trench.