US5640034A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Top-drain trench based resurf DMOS transistor structure
Assignee: Texas Instruments Inc
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Filing: 1992-05-18
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Granted: 1997-06-17
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Expires: 2012-05-18
Abstract
Abstract A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.
Inventors
- 👤 Satwinder Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/663; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10D30/668
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
59 words
A high voltage power transistor, comprising: a source formed at a top surface of the transistor; a drain formed at the top surface of the transistor; a gate formed in a trench between the source and drain; and a nonuniform dielectric lining in the trench having a thin portion adjacent the source and a thick portion adjacent the drain.
Claim 2
Dependent Claim
59 words
A high voltage power transistor, comprising: a source formed at a top surface of the transistor; a drain formed at the top surface of the transistor; a gate formed in a trench between the source and drain; and a nonuniform dielectric lining in the trench having a thin portion adjacent the source and a thick portion adjacent the drain.
Claim 3
Dependent Claim
15 words
The high voltage power transistor of claim 1 wherein the nonuniform dielectric lining is oxide.
Claim 4
Dependent Claim
109 words
A high voltage power transistor, comprising: a substrate; a drift region formed in a top face of the substrate; a drain region formed in the drift region; a p-well region formed in the top face of the substrate; a source region formed in the p-well region; a trench formed in the top face of the substrate between the drift region and the p-well region such that the trench makes contact with both the drift region and the p-well region; a nonuniform dielectric lining in the trench having a thin portion adjacent the p-well region and a thick portion adjacent the drift region; and a gate formed within the trench.
Claim 5
Dependent Claim
109 words
A high voltage power transistor, comprising: a substrate; a drift region formed in a top face of the substrate; a drain region formed in the drift region; a p-well region formed in the top face of the substrate; a source region formed in the p-well region; a trench formed in the top face of the substrate between the drift region and the p-well region such that the trench makes contact with both the drift region and the p-well region; a nonuniform dielectric lining in the trench having a thin portion adjacent the p-well region and a thick portion adjacent the drift region; and a gate formed within the trench.
Claim 6
Dependent Claim
34 words
The high voltage power MOS transistor of claim 3 further comprising an isolation region formed in the face of the substrate below the p-well region to electrically isolate the source region from the substrate.
Claim 7
Dependent Claim
36 words
The high voltage power MOS transistor of claim 4 wherein the substrate and p-well region are P type semiconductor material and the source region, drain region, drift region, and isolation region are N type semiconductor material.
Claim 8
Dependent Claim
60 words
The high voltage power MOS transistor of claim 3 wherein the gate comprises: a nonuniform dielectric lining within the trench, wherein the nonuniform dielectric lining includes a thin portion in the trench adjacent the source region and a thick portion in the trench adjacent the drain region; and a conductive material overlying the nonuniform dielectric and substantially filling the trench.
Claim 9
Dependent Claim
38 words
The high voltage power MOS transistor of claim 6 wherein the nonuniform dielectric comprises: a thin oxide lining on the trench wall adjacent the source; and a thick oxide lining on the trench wall adjacent the drift region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-16 | 2000-12-16 | 2001-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-16 | 2004-12-16 | 2005-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-16 | 2008-12-16 | 2009-06-17 | $7700.00 | Window Closed / Lapsed |