US4949142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated N-channel power MOS bridge circuit
Assignee: STMicroelectronics SRL
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Filing: 1985-09-06
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Granted: 1990-08-14
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Expires: 2005-09-06
Abstract
Abstract The disclosed bridge circuit is fabricated using power MOS technology. Common terminals of the bridge circuit are integrated into common regions in the implementation. Electrodes, typically coupled together in the bridge circuit, are implemented by a shared conducting region in the integrated circuit of the semiconductor chip. By integrating the elements of the circuit, less area of the semiconductor chip is required as compared to an implementation involving 4 (four) discrete elements. Diodes are fabricated across the transistors to protect the elements against reverse biasing.
Inventors
- 👤 Claudio Contiero
- 👤 Paola Galbiati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:34
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/83125
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
163 words
An integrated power MOS bridge circuit comprising, in combination: a semiconductor substrate; first, second and third junction isolated regions of a first conductivity type located in said substrate; junction isolation means in said substrate for laterally separating and electrically isolating said first, second, and third junction isolated regions; first, second and third buried drain layer regions of said first conductivity type in respective ones of said junction isolated regions; a first MOS transistor in said first junction isolated region and a second MOS transistor in said second junction isolated region; third and fourth MOS transistors in said third junction isolated region over said third buried layer region, said third and fourth MOS transistors each including a channel region of a second conductivity type spaced from said junction isolation means; and a sinker region of said first conductivity type in said third junction isolation region, said sinker region extending to said third buried drain layer region between said third and said fourth MOS transistors.
Claim 2
Dependent Claim
163 words
An integrated power MOS bridge circuit comprising, in combination: a semiconductor substrate; first, second and third junction isolated regions of a first conductivity type located in said substrate; junction isolation means in said substrate for laterally separating and electrically isolating said first, second, and third junction isolated regions; first, second and third buried drain layer regions of said first conductivity type in respective ones of said junction isolated regions; a first MOS transistor in said first junction isolated region and a second MOS transistor in said second junction isolated region; third and fourth MOS transistors in said third junction isolated region over said third buried layer region, said third and fourth MOS transistors each including a channel region of a second conductivity type spaced from said junction isolation means; and a sinker region of said first conductivity type in said third junction isolation region, said sinker region extending to said third buried drain layer region between said third and said fourth MOS transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |