Method of making poly LDD self-aligned channel transistors

Claim 1

In a method for making a trench isolated FET wherein an active region in a silicon substrate is isolated by a trench and wherein wells of a first conductivity type in said substrate have separated source and drain regions having top surfaces therein, both said source and drain regions being contiguous to and separated by a gate region, and where in a completed said trench isolated FET said gate region overlies said top surfaces of said source and drain regions adjacent to said contiguous edge by a first distance, the improvement comprising: (a) layering said top of said source and drain regions of said FET with a first poly layer; (b) creating said trench having sidewalls around said source and drain regions by etching into said underlying Si and exposing the edge of said first poly layer without removing said first poly layer overtop said source and drain region; (c) oxidizing said sidewalls of said trench including oxidizing said exposed edge of said first poly layer to form an isolation oxide liner around said periphery of said active region including said source and drain regions, said first poly layer and said trench sidewall having an intersection; (d) depositing an oxide layer over top of said silicon substrate; (e) planarizing said substrate; (f) depositing resist on said substrate and exposing said resist to electromagnetic radiation to pattern said wafer for source and drain contacts and for said gate region; and (g) etching said oxide layer to form said source and drain contact holes and gate openings while maintaining intact said first poly layer and said oxide liner in the vicinity of said intersection.

Claim 6

A method for making a short channel metal-oxide semiconductor device in a semiconductor substrate separated from neighboring devices wherein trenches are formed in said substrate to define each device, said trenches having sidewalls lined with an oxide liner and filled with an oxide filler, wherein said device includes lightly doped source and drain regions and heavily doped source and drain regions having a first conductivity separated by a gate region; a shallow channel doping region having a second conductivity opposite to said first conductivity formed in said gate region; a gate oxide formed over said gate region; a gate electrode comprising doped polysilicon of said first conductivity, said gate electrode having a horizontal and vertical portions, said horizontal portion contacting said gate oxide and said vertical portions extending from said horizontal portion; and doped polysilicon source and drain contacts, said polysilicon source and drain contacts separated from each of said horizontal portion of said gate electrode by oxide regions; the improvement comprising: (a) depositing doped polysilicon layers atop and in contact with said source and drain regions, said polysilicon layers extending beneath said oxide regions and said doped polysilicon source and drain contacts and abutting said oxide liner, said doped polysilicon layers preventing said oxide filler from being overetched to the point of exposing said trench sidewalls during subsequent process steps, thereby preventing the formation of parasitic devices in said sidewalls: and (b) depositing vertical insulation spacers to separate said gate electrode from said oxide regions, wherein said improvement increases the drive currents attainable by said device.

Claim 7

A method for making a short channel metal-oxide semiconductor device in a semiconductor substrate separated from neighboring devices wherein trenches are formed in said substrate to define each device, said trenches having sidewalls lined with an oxide liner and filled with an oxide filler, wherein said device includes lightly doped source and drain regions and heavily doped source and drain regions having a first conductivity separated by a gate region; a shallow channel doping region having a second conductivity opposite to said first conductivity formed in said gate region; a gate oxide formed over said gate region; a gate electrode comprising doped polysilicon of said first conductivity, said gate electrode having a horizontal and vertical portions, said horizontal portion contacting said gate oxide and said vertical portions extending from said horizontal portion; and doped polysilicon source and drain contacts, said polysilicon source and drain contacts separated from each of said horizontal portion of said gate electrode by oxide regions; the improvement comprising: (a) depositing doped polysilicon layers atop and in contact with said source and drain regions, said polysilicon layers extending beneath said oxide regions and said doped polysilicon source and drain contacts and abutting said oxide liner, said doped polysilicon layers preventing said oxide filler from being overetched to the point of exposing said trench sidewalls during subsequent process steps, thereby preventing the formation of parasitic devices in said sidewalls: and (b) depositing vertical insulation spacers to separate said gate electrode from said oxide regions, wherein said improvement increases the drive currents attainable by said device.