Patent US5749088A successfully refreshed from Google Patents.
US5749088A
Expired / Lapsed
US
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Memory card with erasure blocks and circuitry for selectively protecting the blocks from memory operations
Assignee: Intel Corp
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Filing: 1997-04-22
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Granted: 1998-05-05
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Expires: 2017-04-22
Abstract
Abstract A memory card includes a plurality of memories, each having an array that includes a first block and a second block. Control circuitry is coupled to the array for controlling memory operations of the array. A block write protect circuit is provided for storing block lock data to selectively lock control circuitry from accessing the array for the memory operations. The block write protect circuit locks the control circuit from accessing (1) the first block when the block write protect circuit stores a first datum of the data and (2) the second block when the block write protect circuit stores a second datum of the data. A control input is coupled to the block write protect circuit for applying a control signal to enable the block write protect circuit to lock the control circuitry in accordance with the data. The memory card further includes a register circuit coupled to the control input of each of the plurality of memories for storing a control datum to generate the control signal. When the register circuit stores the control datum to generate the control signal, the block write protect circuit of each of the plurality of memories is enabled to lock the respective control circuitry from selectively accessing the respective first and second blocks in accordance with the respective block lock data.
Inventors
- 👤 David M. Brown
- 👤 Russell D. Eslick
- 👤 Kurt B. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:00
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/22
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
326 words
A memory card, comprising: (A) a plurality of nonvolatile memories, each comprising (a) a first and a second individually erasable and programmable memory block; (b) a first and a second nonvolatile memory cell, each storing one of a first and a second datum indicating whether the respective one of the first and second blocks is locked; (c) a first and a second volatile register, each receiving and storing the respective one of the first and second datum when a read operation is performed on the respective one of the first and second memory cells; (d) a block lock circuit that, when enabled, provides a block lock signal in accordance with the first datum in the first register in response to the first block being addressed or the second datum in the second register in response to the second block being addressed to prevent the addressed one of the first and second blocks from being programmed and erased; (e) a control input that applies a control signal to enable the block lock circuit; (B) a register circuit that stores a control datum to generate the control signal to the control input of each of the plurality of nonvolatile memories, wherein when the register circuit does not store the control datum, the block lock circuit of each of the memories is disabled from providing the block lock signal; (C) a card control logic for interfacing the memories with external circuitry, wherein the register circuit is located in the card control logic and is allowed to be updated by the external circuitry with respect to the control datum, and wherein the first memory cell is locked when the first block is locked and the second memory cell is locked when the second block is locked, wherein when the block lock circuit does not receive the control signal, each of the first and second datum stored in each of the first and second memory cells is allowed to be changed.
Claim 2
Dependent Claim
326 words
A memory card, comprising: (A) a plurality of nonvolatile memories, each comprising (a) a first and a second individually erasable and programmable memory block; (b) a first and a second nonvolatile memory cell, each storing one of a first and a second datum indicating whether the respective one of the first and second blocks is locked; (c) a first and a second volatile register, each receiving and storing the respective one of the first and second datum when a read operation is performed on the respective one of the first and second memory cells; (d) a block lock circuit that, when enabled, provides a block lock signal in accordance with the first datum in the first register in response to the first block being addressed or the second datum in the second register in response to the second block being addressed to prevent the addressed one of the first and second blocks from being programmed and erased; (e) a control input that applies a control signal to enable the block lock circuit; (B) a register circuit that stores a control datum to generate the control signal to the control input of each of the plurality of nonvolatile memories, wherein when the register circuit does not store the control datum, the block lock circuit of each of the memories is disabled from providing the block lock signal; (C) a card control logic for interfacing the memories with external circuitry, wherein the register circuit is located in the card control logic and is allowed to be updated by the external circuitry with respect to the control datum, and wherein the first memory cell is locked when the first block is locked and the second memory cell is locked when the second block is locked, wherein when the block lock circuit does not receive the control signal, each of the first and second datum stored in each of the first and second memory cells is allowed to be changed.
Claim 3
Dependent Claim
16 words
The memory card of claim 1, wherein the block lock circuit further comprises a NOR gate.
Claim 4
Dependent Claim
27 words
The memory card of claim 1, wherein the first and second registers receive the first and second datum upon an initiation of power to the memory card.
Claim 5
Dependent Claim
346 words
A computer system, comprising: (A) a central processing unit (CPU); (B) a memory card coupled to the CPU, wherein the memory card further comprises (I) a plurality of nonvolatile memories, each comprising (a) a first and a second individually erasable and programmable memory block; (b) a first and a second nonvolatile memory cell, each storing one of a first and a second datum indicating whether the respective one of the first and second blocks is locked; (c) a first and a second volatile register, each receiving and storing the respective one of the first and second datum when a read operation is performed on the respective one of the first and second memory cells; (d) a block lock circuit that, when enabled, provides a block lock signal in accordance with the first datum in the first register in response to the first block being addressed or the second datum in the second register in response to the second block being addressed to prevent the addressed one of the first and second blocks from being programmed and erased; (e) a control input that applies a control signal to enable the block lock circuit; (II) a register circuit that stores a control datum to generate the control signal to the control input of each of the memories, wherein when the register circuit does not store the control datum, the block lock circuit of each of the memories is disabled from providing the block lock signal; (C) a card control logic for interfacing the plurality of nonvolatile memories with external circuitry, wherein the register circuit is located in the card control logic and is allowed to be updated by the external circuitry with respect to the control datum, and wherein the first memory cell is locked when the first block is locked and the second memory cell is locked when the second block is locked, wherein when the block lock circuit does not receive the control signal, each of the first and second datum stored in each of the first and second memory cells is allowed to be changed.
Claim 6
Dependent Claim
346 words
A computer system, comprising: (A) a central processing unit (CPU); (B) a memory card coupled to the CPU, wherein the memory card further comprises (I) a plurality of nonvolatile memories, each comprising (a) a first and a second individually erasable and programmable memory block; (b) a first and a second nonvolatile memory cell, each storing one of a first and a second datum indicating whether the respective one of the first and second blocks is locked; (c) a first and a second volatile register, each receiving and storing the respective one of the first and second datum when a read operation is performed on the respective one of the first and second memory cells; (d) a block lock circuit that, when enabled, provides a block lock signal in accordance with the first datum in the first register in response to the first block being addressed or the second datum in the second register in response to the second block being addressed to prevent the addressed one of the first and second blocks from being programmed and erased; (e) a control input that applies a control signal to enable the block lock circuit; (II) a register circuit that stores a control datum to generate the control signal to the control input of each of the memories, wherein when the register circuit does not store the control datum, the block lock circuit of each of the memories is disabled from providing the block lock signal; (C) a card control logic for interfacing the plurality of nonvolatile memories with external circuitry, wherein the register circuit is located in the card control logic and is allowed to be updated by the external circuitry with respect to the control datum, and wherein the first memory cell is locked when the first block is locked and the second memory cell is locked when the second block is locked, wherein when the block lock circuit does not receive the control signal, each of the first and second datum stored in each of the first and second memory cells is allowed to be changed.
Claim 7
Dependent Claim
16 words
The computer system of claim 4, wherein the block lock circuit further comprises a NOR gate.
Claim 8
Dependent Claim
27 words
The computer system of claim 4, wherein the first and second registers receive the first and second datum upon an initiation of power to the memory card.
Claim 9
Independent Claim
280 words
A method for use with a plurality of nonvolatile memories each having a first and a second individually erasable and programmable memory block, the method comprising the steps of: (a) storing a first and a second datum in a first and a second nonvolatile memory cell, respectively, the first and second datum indicating whether the respective one of the first and second blocks is locked; (b) receiving and storing in a first and a second volatile register the respective one of the first and second datum when a read operation is performed on the respective one of the first and second memory cells; (c) providing, when a block lock circuit is enabled, a block lock signal in accordance with the first datum in response to the first block being addressed or the second datum in response to the second block being addressed to prevent the addressed one of the first and second blocks from being programmed and erased; (d) applying a control signal to enable the block lock circuit; and (e) storing a control datum to generate the control signal to a control input of each of the plurality of nonvolatile memories, wherein when a register circuit does not store the control datum, the block lock circuit of each of the memories is disabled from providing the block lock signal, wherein the first memory cell is locked when the first block is locked and the second memory cell is locked when the second block is locked, wherein when the block lock circuit does not receive the control signal, each of the first and second datum stored in each of the first and second memory cells is allowed to be changed.
Claim 10
Independent Claim
280 words
A method for use with a plurality of nonvolatile memories each having a first and a second individually erasable and programmable memory block, the method comprising the steps of: (a) storing a first and a second datum in a first and a second nonvolatile memory cell, respectively, the first and second datum indicating whether the respective one of the first and second blocks is locked; (b) receiving and storing in a first and a second volatile register the respective one of the first and second datum when a read operation is performed on the respective one of the first and second memory cells; (c) providing, when a block lock circuit is enabled, a block lock signal in accordance with the first datum in response to the first block being addressed or the second datum in response to the second block being addressed to prevent the addressed one of the first and second blocks from being programmed and erased; (d) applying a control signal to enable the block lock circuit; and (e) storing a control datum to generate the control signal to a control input of each of the plurality of nonvolatile memories, wherein when a register circuit does not store the control datum, the block lock circuit of each of the memories is disabled from providing the block lock signal, wherein the first memory cell is locked when the first block is locked and the second memory cell is locked when the second block is locked, wherein when the block lock circuit does not receive the control signal, each of the first and second datum stored in each of the first and second memory cells is allowed to be changed.
References Cited (Backward Citations)
US4451903A
Cited
US4665506A
Cited
US4811293A
Cited
US4961172A
Cited
US5278786A
Cited
US5065364A
Cited
US5293344A
Cited
US5303198A
Cited
US5386539A
Cited
US5287310A
Cited
US5448712A
Cited
US5249158A
Cited
US5197034A
Cited
US5226006A
Cited
US5361343A
Cited
US5245572A
Cited
US5357573A
Cited
US5224070A
Cited
US5297103A
Cited
US5388248A
Cited
US5267218A
Cited
US5422855A
Cited
US5361228A
Cited
US5280449A
Cited
US5363334A
Cited
US5329491A
Cited
US5369754A
Cited
US5353256A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |