Microprocessor system including first and second nonvolatile memory arrays which may be simultaneously read and reprogrammed

Claim 1

A microprocessor system, comprising: a central processing unit (CPU); a communication port; a bus connected to the CPU and the communication port; a floating gate nonvolatile memory coupled to the CPU and the communication port via the bus, wherein the nonvolatile memory resides on a single silicon substrate, wherein the nonvolatile memory further comprises (a) a first memory array; (b) a first address register for storing a first address for the first memory array; (c) a second memory array; (d) a second address register for storing a second address for the second memory array; (e) a multiplexer having inputs coupled to the first memory array and the second memory array for selectively coupling one of the first memory array and the second memory array to an output of the memory; (f) array select circuitry responsive to (1) incoming array select information associated with the first address and (2) memory operation control information for selecting the first memory array for a reprogramming operation and for allowing a read operation with respect to the second memory array during the reprogramming operation of the first memory array, wherein the array select circuitry is coupled to the CPU via the bus for receiving the array select information and the memory operation control information from the CPU, wherein the array select circuitry directs the first address to the first address register for the reprogramming operation in response to the incoming array select information and the memory operation control information received and directs the second address to the second address register for the read operation during the reprogramming operation of the first memory array, wherein the array select circuitry controls the multiplexer for coupling the second memory array to the output of the memory during the reprogramming operation of the first memory array and the read operation of the second memory array such that the second memory array can be read by the CPU while the first memory array is undergoing the reprogramming operation.